41  * CNL has just one set of registers, while gen11 has a set for each combo PHY.
42  * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
46 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)  in cnl_get_procmon_ref_values()  argument
51 	val = I915_READ(ICL_PORT_COMP_DW3(phy));  in cnl_get_procmon_ref_values()
77 				       enum phy phy)  in cnl_set_procmon_ref_values()  argument
82 	procmon = cnl_get_procmon_ref_values(dev_priv, phy);  in cnl_set_procmon_ref_values()
84 	val = I915_READ(ICL_PORT_COMP_DW1(phy));  in cnl_set_procmon_ref_values()
87 	I915_WRITE(ICL_PORT_COMP_DW1(phy), val);  in cnl_set_procmon_ref_values()
89 	I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9);  in cnl_set_procmon_ref_values()
90 	I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10);  in cnl_set_procmon_ref_values()
94 			  enum phy phy, i915_reg_t reg, u32 mask,  in check_phy_reg()  argument
100 		DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: "  in check_phy_reg()
102 				 phy_name(phy),  in check_phy_reg()
111 					  enum phy phy)  in cnl_verify_procmon_ref_values()  argument
116 	procmon = cnl_get_procmon_ref_values(dev_priv, phy);  in cnl_verify_procmon_ref_values()
118 	ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),  in cnl_verify_procmon_ref_values()
120 	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),  in cnl_verify_procmon_ref_values()
122 	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),  in cnl_verify_procmon_ref_values()
136 	enum phy phy = PHY_A;  in cnl_combo_phy_verify_state()  local
142 	ret = cnl_verify_procmon_ref_values(dev_priv, phy);  in cnl_combo_phy_verify_state()
144 	ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,  in cnl_combo_phy_verify_state()
175 		DRM_WARN("Combo PHY HW state changed unexpectedly.\n");  in cnl_combo_phys_uninit()
183 				  enum phy phy)  in icl_combo_phy_enabled()  argument
185 	/* The PHY C added by EHL has no PHY_MISC register */  in icl_combo_phy_enabled()
186 	if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)  in icl_combo_phy_enabled()
187 		return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT;  in icl_combo_phy_enabled()
189 		return !(I915_READ(ICL_PHY_MISC(phy)) &  in icl_combo_phy_enabled()
191 			(I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT);  in icl_combo_phy_enabled()
195 				       enum phy phy)  in icl_combo_phy_verify_state()  argument
199 	if (!icl_combo_phy_enabled(dev_priv, phy))  in icl_combo_phy_verify_state()
202 	ret = cnl_verify_procmon_ref_values(dev_priv, phy);  in icl_combo_phy_verify_state()
204 	if (phy == PHY_A)  in icl_combo_phy_verify_state()
205 		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),  in icl_combo_phy_verify_state()
208 	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),  in icl_combo_phy_verify_state()
215 				    enum phy phy, bool is_dsi,  in intel_combo_phy_power_up_lanes()  argument
260 	val = I915_READ(ICL_PORT_CL_DW10(phy));  in intel_combo_phy_power_up_lanes()
263 	I915_WRITE(ICL_PORT_CL_DW10(phy), val);  in intel_combo_phy_power_up_lanes()
274 	 * the PHY.  So if combo PHY A is wired up to drive an external  in ehl_combo_phy_a_mux()
287 …DRM_ERROR("VBT claims to have both internal and external displays on PHY A.  Configuring for inter…  in ehl_combo_phy_a_mux()
294 	enum phy phy;  in icl_combo_phys_init()  local
296 	for_each_combo_phy(dev_priv, phy) {  in icl_combo_phys_init()
299 		if (icl_combo_phy_verify_state(dev_priv, phy)) {  in icl_combo_phys_init()
300 			DRM_DEBUG_DRIVER("Combo PHY %c already enabled, won't reprogram it.\n",  in icl_combo_phys_init()
301 					 phy_name(phy));  in icl_combo_phys_init()
306 		 * Although EHL adds a combo PHY C, there's no PHY_MISC  in icl_combo_phys_init()
308 		 * DE_IO_COMP_PWR_DOWN setting on PHY C.  in icl_combo_phys_init()
310 		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)  in icl_combo_phys_init()
314 		 * EHL's combo PHY A can be hooked up to either an external  in icl_combo_phys_init()
317 		 * can't be changed on the fly, so initialize the PHY's mux  in icl_combo_phys_init()
321 		val = I915_READ(ICL_PHY_MISC(phy));  in icl_combo_phys_init()
322 		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A)  in icl_combo_phys_init()
325 		I915_WRITE(ICL_PHY_MISC(phy), val);  in icl_combo_phys_init()
328 		cnl_set_procmon_ref_values(dev_priv, phy);  in icl_combo_phys_init()
330 		if (phy == PHY_A) {  in icl_combo_phys_init()
331 			val = I915_READ(ICL_PORT_COMP_DW8(phy));  in icl_combo_phys_init()
333 			I915_WRITE(ICL_PORT_COMP_DW8(phy), val);  in icl_combo_phys_init()
336 		val = I915_READ(ICL_PORT_COMP_DW0(phy));  in icl_combo_phys_init()
338 		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);  in icl_combo_phys_init()
340 		val = I915_READ(ICL_PORT_CL_DW5(phy));  in icl_combo_phys_init()
342 		I915_WRITE(ICL_PORT_CL_DW5(phy), val);  in icl_combo_phys_init()
348 	enum phy phy;  in icl_combo_phys_uninit()  local
350 	for_each_combo_phy_reverse(dev_priv, phy) {  in icl_combo_phys_uninit()
353 		if (phy == PHY_A &&  in icl_combo_phys_uninit()
354 		    !icl_combo_phy_verify_state(dev_priv, phy))  in icl_combo_phys_uninit()
355 			DRM_WARN("Combo PHY %c HW state changed unexpectedly\n",  in icl_combo_phys_uninit()
356 				 phy_name(phy));  in icl_combo_phys_uninit()
359 		 * Although EHL adds a combo PHY C, there's no PHY_MISC  in icl_combo_phys_uninit()
361 		 * DE_IO_COMP_PWR_DOWN setting on PHY C.  in icl_combo_phys_uninit()
363 		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)  in icl_combo_phys_uninit()
366 		val = I915_READ(ICL_PHY_MISC(phy));  in icl_combo_phys_uninit()
368 		I915_WRITE(ICL_PHY_MISC(phy), val);  in icl_combo_phys_uninit()
371 		val = I915_READ(ICL_PORT_COMP_DW0(phy));  in icl_combo_phys_uninit()
373 		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);  in icl_combo_phys_uninit()