Lines Matching refs:cdclk
59 cdclk_state->cdclk = 133333; in fixed_133mhz_get_cdclk()
65 cdclk_state->cdclk = 200000; in fixed_200mhz_get_cdclk()
71 cdclk_state->cdclk = 266667; in fixed_266mhz_get_cdclk()
77 cdclk_state->cdclk = 333333; in fixed_333mhz_get_cdclk()
83 cdclk_state->cdclk = 400000; in fixed_400mhz_get_cdclk()
89 cdclk_state->cdclk = 450000; in fixed_450mhz_get_cdclk()
104 cdclk_state->cdclk = 133333; in i85x_get_cdclk()
118 cdclk_state->cdclk = 200000; in i85x_get_cdclk()
121 cdclk_state->cdclk = 250000; in i85x_get_cdclk()
124 cdclk_state->cdclk = 133333; in i85x_get_cdclk()
129 cdclk_state->cdclk = 266667; in i85x_get_cdclk()
143 cdclk_state->cdclk = 133333; in i915gm_get_cdclk()
149 cdclk_state->cdclk = 333333; in i915gm_get_cdclk()
153 cdclk_state->cdclk = 190000; in i915gm_get_cdclk()
167 cdclk_state->cdclk = 133333; in i945gm_get_cdclk()
173 cdclk_state->cdclk = 320000; in i945gm_get_cdclk()
177 cdclk_state->cdclk = 200000; in i945gm_get_cdclk()
289 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, in g33_get_cdclk()
296 cdclk_state->cdclk = 190476; in g33_get_cdclk()
309 cdclk_state->cdclk = 266667; in pnv_get_cdclk()
312 cdclk_state->cdclk = 333333; in pnv_get_cdclk()
315 cdclk_state->cdclk = 444444; in pnv_get_cdclk()
318 cdclk_state->cdclk = 200000; in pnv_get_cdclk()
324 cdclk_state->cdclk = 133333; in pnv_get_cdclk()
327 cdclk_state->cdclk = 166667; in pnv_get_cdclk()
366 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, in i965gm_get_cdclk()
373 cdclk_state->cdclk = 200000; in i965gm_get_cdclk()
393 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
396 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
401 cdclk_state->cdclk = 222222; in gm45_get_cdclk()
413 cdclk_state->cdclk = 800000; in hsw_get_cdclk()
415 cdclk_state->cdclk = 450000; in hsw_get_cdclk()
417 cdclk_state->cdclk = 450000; in hsw_get_cdclk()
419 cdclk_state->cdclk = 337500; in hsw_get_cdclk()
421 cdclk_state->cdclk = 540000; in hsw_get_cdclk()
444 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) in vlv_calc_voltage_level() argument
447 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ in vlv_calc_voltage_level()
449 else if (cdclk >= 266667) in vlv_calc_voltage_level()
459 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
472 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
498 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
529 int cdclk = cdclk_state->cdclk; in vlv_set_cdclk() local
533 switch (cdclk) { in vlv_set_cdclk()
541 MISSING_CASE(cdclk); in vlv_set_cdclk()
568 if (cdclk == 400000) { in vlv_set_cdclk()
572 cdclk) - 1; in vlv_set_cdclk()
594 if (cdclk == 400000) in vlv_set_cdclk()
616 int cdclk = cdclk_state->cdclk; in chv_set_cdclk() local
620 switch (cdclk) { in chv_set_cdclk()
627 MISSING_CASE(cdclk); in chv_set_cdclk()
671 static u8 bdw_calc_voltage_level(int cdclk) in bdw_calc_voltage_level() argument
673 switch (cdclk) { in bdw_calc_voltage_level()
693 cdclk_state->cdclk = 800000; in bdw_get_cdclk()
695 cdclk_state->cdclk = 450000; in bdw_get_cdclk()
697 cdclk_state->cdclk = 450000; in bdw_get_cdclk()
699 cdclk_state->cdclk = 540000; in bdw_get_cdclk()
701 cdclk_state->cdclk = 337500; in bdw_get_cdclk()
703 cdclk_state->cdclk = 675000; in bdw_get_cdclk()
710 bdw_calc_voltage_level(cdclk_state->cdclk); in bdw_get_cdclk()
717 int cdclk = cdclk_state->cdclk; in bdw_set_cdclk() local
751 switch (cdclk) { in bdw_set_cdclk()
753 MISSING_CASE(cdclk); in bdw_set_cdclk()
782 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
810 static u8 skl_calc_voltage_level(int cdclk) in skl_calc_voltage_level() argument
812 if (cdclk > 540000) in skl_calc_voltage_level()
814 else if (cdclk > 450000) in skl_calc_voltage_level()
816 else if (cdclk > 337500) in skl_calc_voltage_level()
869 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; in skl_get_cdclk()
879 cdclk_state->cdclk = 432000; in skl_get_cdclk()
882 cdclk_state->cdclk = 308571; in skl_get_cdclk()
885 cdclk_state->cdclk = 540000; in skl_get_cdclk()
888 cdclk_state->cdclk = 617143; in skl_get_cdclk()
897 cdclk_state->cdclk = 450000; in skl_get_cdclk()
900 cdclk_state->cdclk = 337500; in skl_get_cdclk()
903 cdclk_state->cdclk = 540000; in skl_get_cdclk()
906 cdclk_state->cdclk = 675000; in skl_get_cdclk()
920 skl_calc_voltage_level(cdclk_state->cdclk); in skl_get_cdclk()
924 static int skl_cdclk_decimal(int cdclk) in skl_cdclk_decimal() argument
926 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); in skl_cdclk_decimal()
975 dev_priv->cdclk.hw.vco = vco; in skl_dpll0_enable()
987 dev_priv->cdclk.hw.vco = 0; in skl_dpll0_disable()
994 int cdclk = cdclk_state->cdclk; in skl_set_cdclk() local
1020 switch (cdclk) { in skl_set_cdclk()
1022 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); in skl_set_cdclk()
1042 if (dev_priv->cdclk.hw.vco != 0 && in skl_set_cdclk()
1043 dev_priv->cdclk.hw.vco != vco) in skl_set_cdclk()
1048 if (dev_priv->cdclk.hw.vco != vco) { in skl_set_cdclk()
1051 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); in skl_set_cdclk()
1060 if (dev_priv->cdclk.hw.vco != vco) in skl_set_cdclk()
1067 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); in skl_set_cdclk()
1095 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1098 if (dev_priv->cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1099 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in skl_sanitize_cdclk()
1110 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); in skl_sanitize_cdclk()
1119 dev_priv->cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1121 dev_priv->cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1130 if (dev_priv->cdclk.hw.cdclk != 0 && in skl_init_cdclk()
1131 dev_priv->cdclk.hw.vco != 0) { in skl_init_cdclk()
1138 dev_priv->cdclk.hw.vco); in skl_init_cdclk()
1142 cdclk_state = dev_priv->cdclk.hw; in skl_init_cdclk()
1147 cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco); in skl_init_cdclk()
1148 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); in skl_init_cdclk()
1155 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; in skl_uninit_cdclk()
1157 cdclk_state.cdclk = cdclk_state.bypass; in skl_uninit_cdclk()
1159 cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); in skl_uninit_cdclk()
1188 static u8 bxt_calc_voltage_level(int cdclk) in bxt_calc_voltage_level() argument
1190 return DIV_ROUND_UP(cdclk, 25000); in bxt_calc_voltage_level()
1193 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in bxt_de_pll_vco() argument
1197 if (cdclk == dev_priv->cdclk.hw.bypass) in bxt_de_pll_vco()
1200 switch (cdclk) { in bxt_de_pll_vco()
1202 MISSING_CASE(cdclk); in bxt_de_pll_vco()
1215 return dev_priv->cdclk.hw.ref * ratio; in bxt_de_pll_vco()
1218 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in glk_de_pll_vco() argument
1222 if (cdclk == dev_priv->cdclk.hw.bypass) in glk_de_pll_vco()
1225 switch (cdclk) { in glk_de_pll_vco()
1227 MISSING_CASE(cdclk); in glk_de_pll_vco()
1236 return dev_priv->cdclk.hw.ref * ratio; in glk_de_pll_vco()
1266 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; in bxt_get_cdclk()
1292 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); in bxt_get_cdclk()
1300 bxt_calc_voltage_level(cdclk_state->cdclk); in bxt_get_cdclk()
1312 dev_priv->cdclk.hw.vco = 0; in bxt_de_pll_disable()
1317 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in bxt_de_pll_enable()
1332 dev_priv->cdclk.hw.vco = vco; in bxt_de_pll_enable()
1339 int cdclk = cdclk_state->cdclk; in bxt_set_cdclk() local
1345 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { in bxt_set_cdclk()
1347 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); in bxt_set_cdclk()
1375 ret, cdclk); in bxt_set_cdclk()
1379 if (dev_priv->cdclk.hw.vco != 0 && in bxt_set_cdclk()
1380 dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1383 if (dev_priv->cdclk.hw.vco != vco) in bxt_set_cdclk()
1386 val = divider | skl_cdclk_decimal(cdclk); in bxt_set_cdclk()
1395 if (cdclk >= 500000) in bxt_set_cdclk()
1413 ret, cdclk); in bxt_set_cdclk()
1425 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1427 if (dev_priv->cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1428 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in bxt_sanitize_cdclk()
1446 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
1451 if (dev_priv->cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
1462 dev_priv->cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
1465 dev_priv->cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
1474 if (dev_priv->cdclk.hw.cdclk != 0 && in bxt_init_cdclk()
1475 dev_priv->cdclk.hw.vco != 0) in bxt_init_cdclk()
1478 cdclk_state = dev_priv->cdclk.hw; in bxt_init_cdclk()
1486 cdclk_state.cdclk = glk_calc_cdclk(0); in bxt_init_cdclk()
1487 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk); in bxt_init_cdclk()
1489 cdclk_state.cdclk = bxt_calc_cdclk(0); in bxt_init_cdclk()
1490 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk); in bxt_init_cdclk()
1492 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk); in bxt_init_cdclk()
1499 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; in bxt_uninit_cdclk()
1501 cdclk_state.cdclk = cdclk_state.bypass; in bxt_uninit_cdclk()
1503 cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk); in bxt_uninit_cdclk()
1518 static u8 cnl_calc_voltage_level(int cdclk) in cnl_calc_voltage_level() argument
1520 if (cdclk > 336000) in cnl_calc_voltage_level()
1522 else if (cdclk > 168000) in cnl_calc_voltage_level()
1558 cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; in cnl_get_cdclk()
1577 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); in cnl_get_cdclk()
1585 cnl_calc_voltage_level(cdclk_state->cdclk); in cnl_get_cdclk()
1600 dev_priv->cdclk.hw.vco = 0; in cnl_cdclk_pll_disable()
1605 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); in cnl_cdclk_pll_enable()
1618 dev_priv->cdclk.hw.vco = vco; in cnl_cdclk_pll_enable()
1625 int cdclk = cdclk_state->cdclk; in cnl_set_cdclk() local
1641 switch (DIV_ROUND_CLOSEST(vco, cdclk)) { in cnl_set_cdclk()
1643 WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); in cnl_set_cdclk()
1654 if (dev_priv->cdclk.hw.vco != 0 && in cnl_set_cdclk()
1655 dev_priv->cdclk.hw.vco != vco) in cnl_set_cdclk()
1658 if (dev_priv->cdclk.hw.vco != vco) in cnl_set_cdclk()
1661 val = divider | skl_cdclk_decimal(cdclk); in cnl_set_cdclk()
1681 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; in cnl_set_cdclk()
1684 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in cnl_cdclk_pll_vco() argument
1688 if (cdclk == dev_priv->cdclk.hw.bypass) in cnl_cdclk_pll_vco()
1691 switch (cdclk) { in cnl_cdclk_pll_vco()
1693 MISSING_CASE(cdclk); in cnl_cdclk_pll_vco()
1697 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28; in cnl_cdclk_pll_vco()
1700 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44; in cnl_cdclk_pll_vco()
1704 return dev_priv->cdclk.hw.ref * ratio; in cnl_cdclk_pll_vco()
1712 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); in cnl_sanitize_cdclk()
1714 if (dev_priv->cdclk.hw.vco == 0 || in cnl_sanitize_cdclk()
1715 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in cnl_sanitize_cdclk()
1733 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); in cnl_sanitize_cdclk()
1743 dev_priv->cdclk.hw.cdclk = 0; in cnl_sanitize_cdclk()
1746 dev_priv->cdclk.hw.vco = -1; in cnl_sanitize_cdclk()
1780 static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in icl_calc_cdclk_pll_vco() argument
1784 if (cdclk == dev_priv->cdclk.hw.bypass) in icl_calc_cdclk_pll_vco()
1787 switch (cdclk) { in icl_calc_cdclk_pll_vco()
1789 MISSING_CASE(cdclk); in icl_calc_cdclk_pll_vco()
1795 WARN_ON(dev_priv->cdclk.hw.ref != 19200 && in icl_calc_cdclk_pll_vco()
1796 dev_priv->cdclk.hw.ref != 38400); in icl_calc_cdclk_pll_vco()
1802 WARN_ON(dev_priv->cdclk.hw.ref != 24000); in icl_calc_cdclk_pll_vco()
1805 WARN_ON(dev_priv->cdclk.hw.ref != 19200 && in icl_calc_cdclk_pll_vco()
1806 dev_priv->cdclk.hw.ref != 38400 && in icl_calc_cdclk_pll_vco()
1807 dev_priv->cdclk.hw.ref != 24000); in icl_calc_cdclk_pll_vco()
1811 ratio = cdclk / (dev_priv->cdclk.hw.ref / 2); in icl_calc_cdclk_pll_vco()
1813 return dev_priv->cdclk.hw.ref * ratio; in icl_calc_cdclk_pll_vco()
1820 unsigned int cdclk = cdclk_state->cdclk; in icl_set_cdclk() local
1834 if (dev_priv->cdclk.hw.vco != 0 && in icl_set_cdclk()
1835 dev_priv->cdclk.hw.vco != vco) in icl_set_cdclk()
1838 if (dev_priv->cdclk.hw.vco != vco) in icl_set_cdclk()
1847 skl_cdclk_decimal(cdclk)); in icl_set_cdclk()
1858 dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; in icl_set_cdclk()
1861 static u8 icl_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) in icl_calc_voltage_level() argument
1864 if (cdclk > 312000) in icl_calc_voltage_level()
1866 else if (cdclk > 180000) in icl_calc_voltage_level()
1871 if (cdclk > 556800) in icl_calc_voltage_level()
1873 else if (cdclk > 312000) in icl_calc_voltage_level()
1911 cdclk_state->cdclk = cdclk_state->bypass; in icl_get_cdclk()
1920 cdclk_state->cdclk = cdclk_state->vco / 2; in icl_get_cdclk()
1928 icl_calc_voltage_level(dev_priv, cdclk_state->cdclk); in icl_get_cdclk()
1938 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); in icl_init_cdclk()
1941 if (dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) in icl_init_cdclk()
1950 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk)) in icl_init_cdclk()
1958 sanitized_state.ref = dev_priv->cdclk.hw.ref; in icl_init_cdclk()
1959 sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref); in icl_init_cdclk()
1961 sanitized_state.cdclk); in icl_init_cdclk()
1964 sanitized_state.cdclk); in icl_init_cdclk()
1971 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; in icl_uninit_cdclk()
1973 cdclk_state.cdclk = cdclk_state.bypass; in icl_uninit_cdclk()
1976 cdclk_state.cdclk); in icl_uninit_cdclk()
1987 if (dev_priv->cdclk.hw.cdclk != 0 && in cnl_init_cdclk()
1988 dev_priv->cdclk.hw.vco != 0) in cnl_init_cdclk()
1991 cdclk_state = dev_priv->cdclk.hw; in cnl_init_cdclk()
1993 cdclk_state.cdclk = cnl_calc_cdclk(0); in cnl_init_cdclk()
1994 cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); in cnl_init_cdclk()
1995 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk); in cnl_init_cdclk()
2002 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; in cnl_uninit_cdclk()
2004 cdclk_state.cdclk = cdclk_state.bypass; in cnl_uninit_cdclk()
2006 cdclk_state.voltage_level = cnl_calc_voltage_level(cdclk_state.cdclk); in cnl_uninit_cdclk()
2062 return a->cdclk != b->cdclk || in intel_cdclk_needs_modeset()
2084 return a->cdclk != b->cdclk && in intel_cdclk_needs_cd2x_update()
2120 swap(state->cdclk.logical, dev_priv->cdclk.logical); in intel_cdclk_swap_state()
2121 swap(state->cdclk.actual, dev_priv->cdclk.actual); in intel_cdclk_swap_state()
2128 context, cdclk_state->cdclk, cdclk_state->vco, in intel_dump_cdclk_state()
2146 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state)) in intel_set_cdclk()
2156 if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state), in intel_set_cdclk()
2158 intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]"); in intel_set_cdclk()
2179 if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk) in intel_set_cdclk_pre_plane_update()
2199 if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk) in intel_set_cdclk_post_plane_update()
2313 min_cdclk = state->cdclk.force_min_cdclk; in intel_compute_min_cdclk()
2360 int min_cdclk, cdclk; in vlv_modeset_calc_cdclk() local
2366 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); in vlv_modeset_calc_cdclk()
2368 state->cdclk.logical.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2369 state->cdclk.logical.voltage_level = in vlv_modeset_calc_cdclk()
2370 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2373 cdclk = vlv_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk); in vlv_modeset_calc_cdclk()
2375 state->cdclk.actual.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2376 state->cdclk.actual.voltage_level = in vlv_modeset_calc_cdclk()
2377 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2379 state->cdclk.actual = state->cdclk.logical; in vlv_modeset_calc_cdclk()
2387 int min_cdclk, cdclk; in bdw_modeset_calc_cdclk() local
2397 cdclk = bdw_calc_cdclk(min_cdclk); in bdw_modeset_calc_cdclk()
2399 state->cdclk.logical.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2400 state->cdclk.logical.voltage_level = in bdw_modeset_calc_cdclk()
2401 bdw_calc_voltage_level(cdclk); in bdw_modeset_calc_cdclk()
2404 cdclk = bdw_calc_cdclk(state->cdclk.force_min_cdclk); in bdw_modeset_calc_cdclk()
2406 state->cdclk.actual.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2407 state->cdclk.actual.voltage_level = in bdw_modeset_calc_cdclk()
2408 bdw_calc_voltage_level(cdclk); in bdw_modeset_calc_cdclk()
2410 state->cdclk.actual = state->cdclk.logical; in bdw_modeset_calc_cdclk()
2423 vco = state->cdclk.logical.vco; in skl_dpll0_vco()
2454 int min_cdclk, cdclk, vco; in skl_modeset_calc_cdclk() local
2466 cdclk = skl_calc_cdclk(min_cdclk, vco); in skl_modeset_calc_cdclk()
2468 state->cdclk.logical.vco = vco; in skl_modeset_calc_cdclk()
2469 state->cdclk.logical.cdclk = cdclk; in skl_modeset_calc_cdclk()
2470 state->cdclk.logical.voltage_level = in skl_modeset_calc_cdclk()
2471 skl_calc_voltage_level(cdclk); in skl_modeset_calc_cdclk()
2474 cdclk = skl_calc_cdclk(state->cdclk.force_min_cdclk, vco); in skl_modeset_calc_cdclk()
2476 state->cdclk.actual.vco = vco; in skl_modeset_calc_cdclk()
2477 state->cdclk.actual.cdclk = cdclk; in skl_modeset_calc_cdclk()
2478 state->cdclk.actual.voltage_level = in skl_modeset_calc_cdclk()
2479 skl_calc_voltage_level(cdclk); in skl_modeset_calc_cdclk()
2481 state->cdclk.actual = state->cdclk.logical; in skl_modeset_calc_cdclk()
2490 int min_cdclk, cdclk, vco; in bxt_modeset_calc_cdclk() local
2497 cdclk = glk_calc_cdclk(min_cdclk); in bxt_modeset_calc_cdclk()
2498 vco = glk_de_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2500 cdclk = bxt_calc_cdclk(min_cdclk); in bxt_modeset_calc_cdclk()
2501 vco = bxt_de_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2504 state->cdclk.logical.vco = vco; in bxt_modeset_calc_cdclk()
2505 state->cdclk.logical.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2506 state->cdclk.logical.voltage_level = in bxt_modeset_calc_cdclk()
2507 bxt_calc_voltage_level(cdclk); in bxt_modeset_calc_cdclk()
2511 cdclk = glk_calc_cdclk(state->cdclk.force_min_cdclk); in bxt_modeset_calc_cdclk()
2512 vco = glk_de_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2514 cdclk = bxt_calc_cdclk(state->cdclk.force_min_cdclk); in bxt_modeset_calc_cdclk()
2515 vco = bxt_de_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
2518 state->cdclk.actual.vco = vco; in bxt_modeset_calc_cdclk()
2519 state->cdclk.actual.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2520 state->cdclk.actual.voltage_level = in bxt_modeset_calc_cdclk()
2521 bxt_calc_voltage_level(cdclk); in bxt_modeset_calc_cdclk()
2523 state->cdclk.actual = state->cdclk.logical; in bxt_modeset_calc_cdclk()
2532 int min_cdclk, cdclk, vco; in cnl_modeset_calc_cdclk() local
2538 cdclk = cnl_calc_cdclk(min_cdclk); in cnl_modeset_calc_cdclk()
2539 vco = cnl_cdclk_pll_vco(dev_priv, cdclk); in cnl_modeset_calc_cdclk()
2541 state->cdclk.logical.vco = vco; in cnl_modeset_calc_cdclk()
2542 state->cdclk.logical.cdclk = cdclk; in cnl_modeset_calc_cdclk()
2543 state->cdclk.logical.voltage_level = in cnl_modeset_calc_cdclk()
2544 max(cnl_calc_voltage_level(cdclk), in cnl_modeset_calc_cdclk()
2548 cdclk = cnl_calc_cdclk(state->cdclk.force_min_cdclk); in cnl_modeset_calc_cdclk()
2549 vco = cnl_cdclk_pll_vco(dev_priv, cdclk); in cnl_modeset_calc_cdclk()
2551 state->cdclk.actual.vco = vco; in cnl_modeset_calc_cdclk()
2552 state->cdclk.actual.cdclk = cdclk; in cnl_modeset_calc_cdclk()
2553 state->cdclk.actual.voltage_level = in cnl_modeset_calc_cdclk()
2554 cnl_calc_voltage_level(cdclk); in cnl_modeset_calc_cdclk()
2556 state->cdclk.actual = state->cdclk.logical; in cnl_modeset_calc_cdclk()
2565 unsigned int ref = state->cdclk.logical.ref; in icl_modeset_calc_cdclk()
2566 int min_cdclk, cdclk, vco; in icl_modeset_calc_cdclk() local
2572 cdclk = icl_calc_cdclk(min_cdclk, ref); in icl_modeset_calc_cdclk()
2573 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk); in icl_modeset_calc_cdclk()
2575 state->cdclk.logical.vco = vco; in icl_modeset_calc_cdclk()
2576 state->cdclk.logical.cdclk = cdclk; in icl_modeset_calc_cdclk()
2577 state->cdclk.logical.voltage_level = in icl_modeset_calc_cdclk()
2578 max(icl_calc_voltage_level(dev_priv, cdclk), in icl_modeset_calc_cdclk()
2582 cdclk = icl_calc_cdclk(state->cdclk.force_min_cdclk, ref); in icl_modeset_calc_cdclk()
2583 vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk); in icl_modeset_calc_cdclk()
2585 state->cdclk.actual.vco = vco; in icl_modeset_calc_cdclk()
2586 state->cdclk.actual.cdclk = cdclk; in icl_modeset_calc_cdclk()
2587 state->cdclk.actual.voltage_level = in icl_modeset_calc_cdclk()
2588 icl_calc_voltage_level(dev_priv, cdclk); in icl_modeset_calc_cdclk()
2590 state->cdclk.actual = state->cdclk.logical; in icl_modeset_calc_cdclk()
2624 if (dev_priv->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2629 if (dev_priv->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
2682 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; in intel_update_max_cdclk()
2702 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw); in intel_update_cdclk()
2712 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); in intel_update_cdclk()