Lines Matching refs:tmp
127 u32 tmp = 0; in add_payld_to_queue() local
136 tmp |= *data++ << 8 * j; in add_payld_to_queue()
138 I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp); in add_payld_to_queue()
150 u32 tmp; in dsi_send_pkt_hdr() local
160 tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans)); in dsi_send_pkt_hdr()
163 tmp |= PAYLOAD_PRESENT; in dsi_send_pkt_hdr()
165 tmp &= ~PAYLOAD_PRESENT; in dsi_send_pkt_hdr()
167 tmp &= ~VBLANK_FENCE; in dsi_send_pkt_hdr()
170 tmp |= LP_DATA_TRANSFER; in dsi_send_pkt_hdr()
172 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); in dsi_send_pkt_hdr()
173 tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT); in dsi_send_pkt_hdr()
174 tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT); in dsi_send_pkt_hdr()
175 tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT); in dsi_send_pkt_hdr()
176 tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT); in dsi_send_pkt_hdr()
177 I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp); in dsi_send_pkt_hdr()
206 u32 tmp; in dsi_program_swing_and_deemphasis() local
214 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); in dsi_program_swing_and_deemphasis()
215 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); in dsi_program_swing_and_deemphasis()
216 tmp |= SCALING_MODE_SEL(0x2); in dsi_program_swing_and_deemphasis()
217 tmp |= TAP2_DISABLE | TAP3_DISABLE; in dsi_program_swing_and_deemphasis()
218 tmp |= RTERM_SELECT(0x6); in dsi_program_swing_and_deemphasis()
219 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
221 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); in dsi_program_swing_and_deemphasis()
222 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); in dsi_program_swing_and_deemphasis()
223 tmp |= SCALING_MODE_SEL(0x2); in dsi_program_swing_and_deemphasis()
224 tmp |= TAP2_DISABLE | TAP3_DISABLE; in dsi_program_swing_and_deemphasis()
225 tmp |= RTERM_SELECT(0x6); in dsi_program_swing_and_deemphasis()
226 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
228 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); in dsi_program_swing_and_deemphasis()
229 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | in dsi_program_swing_and_deemphasis()
231 tmp |= SWING_SEL_UPPER(0x2); in dsi_program_swing_and_deemphasis()
232 tmp |= SWING_SEL_LOWER(0x2); in dsi_program_swing_and_deemphasis()
233 tmp |= RCOMP_SCALAR(0x98); in dsi_program_swing_and_deemphasis()
234 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); in dsi_program_swing_and_deemphasis()
236 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); in dsi_program_swing_and_deemphasis()
237 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | in dsi_program_swing_and_deemphasis()
239 tmp |= SWING_SEL_UPPER(0x2); in dsi_program_swing_and_deemphasis()
240 tmp |= SWING_SEL_LOWER(0x2); in dsi_program_swing_and_deemphasis()
241 tmp |= RCOMP_SCALAR(0x98); in dsi_program_swing_and_deemphasis()
242 I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
244 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); in dsi_program_swing_and_deemphasis()
245 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | in dsi_program_swing_and_deemphasis()
247 tmp |= POST_CURSOR_1(0x0); in dsi_program_swing_and_deemphasis()
248 tmp |= POST_CURSOR_2(0x0); in dsi_program_swing_and_deemphasis()
249 tmp |= CURSOR_COEFF(0x3f); in dsi_program_swing_and_deemphasis()
250 I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); in dsi_program_swing_and_deemphasis()
254 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); in dsi_program_swing_and_deemphasis()
255 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | in dsi_program_swing_and_deemphasis()
257 tmp |= POST_CURSOR_1(0x0); in dsi_program_swing_and_deemphasis()
258 tmp |= POST_CURSOR_2(0x0); in dsi_program_swing_and_deemphasis()
259 tmp |= CURSOR_COEFF(0x3f); in dsi_program_swing_and_deemphasis()
260 I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); in dsi_program_swing_and_deemphasis()
351 u32 tmp; in gen11_dsi_enable_io_power() local
354 tmp = I915_READ(ICL_DSI_IO_MODECTL(port)); in gen11_dsi_enable_io_power()
355 tmp |= COMBO_PHY_MODE_DSI; in gen11_dsi_enable_io_power()
356 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp); in gen11_dsi_enable_io_power()
378 u32 tmp; in gen11_dsi_config_phy_lanes_sequence() local
383 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); in gen11_dsi_config_phy_lanes_sequence()
384 tmp &= ~LOADGEN_SELECT; in gen11_dsi_config_phy_lanes_sequence()
385 I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); in gen11_dsi_config_phy_lanes_sequence()
387 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); in gen11_dsi_config_phy_lanes_sequence()
388 tmp &= ~LOADGEN_SELECT; in gen11_dsi_config_phy_lanes_sequence()
390 tmp |= LOADGEN_SELECT; in gen11_dsi_config_phy_lanes_sequence()
391 I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); in gen11_dsi_config_phy_lanes_sequence()
397 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); in gen11_dsi_config_phy_lanes_sequence()
398 tmp &= ~FRC_LATENCY_OPTIM_MASK; in gen11_dsi_config_phy_lanes_sequence()
399 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); in gen11_dsi_config_phy_lanes_sequence()
400 I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); in gen11_dsi_config_phy_lanes_sequence()
401 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); in gen11_dsi_config_phy_lanes_sequence()
402 tmp &= ~FRC_LATENCY_OPTIM_MASK; in gen11_dsi_config_phy_lanes_sequence()
403 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); in gen11_dsi_config_phy_lanes_sequence()
404 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); in gen11_dsi_config_phy_lanes_sequence()
408 tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); in gen11_dsi_config_phy_lanes_sequence()
409 tmp &= ~LATENCY_OPTIM_MASK; in gen11_dsi_config_phy_lanes_sequence()
410 tmp |= LATENCY_OPTIM_VAL(0); in gen11_dsi_config_phy_lanes_sequence()
411 I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); in gen11_dsi_config_phy_lanes_sequence()
413 tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); in gen11_dsi_config_phy_lanes_sequence()
414 tmp &= ~LATENCY_OPTIM_MASK; in gen11_dsi_config_phy_lanes_sequence()
415 tmp |= LATENCY_OPTIM_VAL(0x1); in gen11_dsi_config_phy_lanes_sequence()
416 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); in gen11_dsi_config_phy_lanes_sequence()
426 u32 tmp; in gen11_dsi_voltage_swing_program_seq() local
431 tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); in gen11_dsi_voltage_swing_program_seq()
432 tmp &= ~COMMON_KEEPER_EN; in gen11_dsi_voltage_swing_program_seq()
433 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); in gen11_dsi_voltage_swing_program_seq()
434 tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); in gen11_dsi_voltage_swing_program_seq()
435 tmp &= ~COMMON_KEEPER_EN; in gen11_dsi_voltage_swing_program_seq()
436 I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); in gen11_dsi_voltage_swing_program_seq()
445 tmp = I915_READ(ICL_PORT_CL_DW5(phy)); in gen11_dsi_voltage_swing_program_seq()
446 tmp |= SUS_CLOCK_CONFIG; in gen11_dsi_voltage_swing_program_seq()
447 I915_WRITE(ICL_PORT_CL_DW5(phy), tmp); in gen11_dsi_voltage_swing_program_seq()
452 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); in gen11_dsi_voltage_swing_program_seq()
453 tmp &= ~TX_TRAINING_EN; in gen11_dsi_voltage_swing_program_seq()
454 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); in gen11_dsi_voltage_swing_program_seq()
455 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); in gen11_dsi_voltage_swing_program_seq()
456 tmp &= ~TX_TRAINING_EN; in gen11_dsi_voltage_swing_program_seq()
457 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); in gen11_dsi_voltage_swing_program_seq()
465 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); in gen11_dsi_voltage_swing_program_seq()
466 tmp |= TX_TRAINING_EN; in gen11_dsi_voltage_swing_program_seq()
467 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); in gen11_dsi_voltage_swing_program_seq()
468 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); in gen11_dsi_voltage_swing_program_seq()
469 tmp |= TX_TRAINING_EN; in gen11_dsi_voltage_swing_program_seq()
470 I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); in gen11_dsi_voltage_swing_program_seq()
478 u32 tmp; in gen11_dsi_enable_ddi_buffer() local
482 tmp = I915_READ(DDI_BUF_CTL(port)); in gen11_dsi_enable_ddi_buffer()
483 tmp |= DDI_BUF_CTL_ENABLE; in gen11_dsi_enable_ddi_buffer()
484 I915_WRITE(DDI_BUF_CTL(port), tmp); in gen11_dsi_enable_ddi_buffer()
497 u32 tmp; in gen11_dsi_setup_dphy_timings() local
503 tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port)); in gen11_dsi_setup_dphy_timings()
504 tmp &= ~MASTER_INIT_TIMER_MASK; in gen11_dsi_setup_dphy_timings()
505 tmp |= intel_dsi->init_count; in gen11_dsi_setup_dphy_timings()
506 I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp); in gen11_dsi_setup_dphy_timings()
536 tmp = I915_READ(DPHY_TA_TIMING_PARAM(port)); in gen11_dsi_setup_dphy_timings()
537 tmp &= ~TA_SURE_MASK; in gen11_dsi_setup_dphy_timings()
538 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); in gen11_dsi_setup_dphy_timings()
539 I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp); in gen11_dsi_setup_dphy_timings()
542 tmp = I915_READ(DSI_TA_TIMING_PARAM(port)); in gen11_dsi_setup_dphy_timings()
543 tmp &= ~TA_SURE_MASK; in gen11_dsi_setup_dphy_timings()
544 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); in gen11_dsi_setup_dphy_timings()
545 I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp); in gen11_dsi_setup_dphy_timings()
552 tmp = I915_READ(ICL_DPHY_CHKN(phy)); in gen11_dsi_setup_dphy_timings()
553 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; in gen11_dsi_setup_dphy_timings()
554 I915_WRITE(ICL_DPHY_CHKN(phy), tmp); in gen11_dsi_setup_dphy_timings()
563 u32 tmp; in gen11_dsi_gate_clocks() local
567 tmp = I915_READ(ICL_DPCLKA_CFGCR0); in gen11_dsi_gate_clocks()
569 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); in gen11_dsi_gate_clocks()
571 I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); in gen11_dsi_gate_clocks()
579 u32 tmp; in gen11_dsi_ungate_clocks() local
583 tmp = I915_READ(ICL_DPCLKA_CFGCR0); in gen11_dsi_ungate_clocks()
585 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); in gen11_dsi_ungate_clocks()
587 I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); in gen11_dsi_ungate_clocks()
630 u32 tmp; in gen11_dsi_configure_transcoder() local
636 tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)); in gen11_dsi_configure_transcoder()
639 tmp &= ~EOTP_DISABLED; in gen11_dsi_configure_transcoder()
641 tmp |= EOTP_DISABLED; in gen11_dsi_configure_transcoder()
645 tmp &= ~LINK_CALIBRATION_MASK; in gen11_dsi_configure_transcoder()
646 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; in gen11_dsi_configure_transcoder()
650 tmp &= ~CONTINUOUS_CLK_MASK; in gen11_dsi_configure_transcoder()
652 tmp |= CLK_ENTER_LP_AFTER_DATA; in gen11_dsi_configure_transcoder()
654 tmp |= CLK_HS_CONTINUOUS; in gen11_dsi_configure_transcoder()
657 tmp &= ~PIX_BUF_THRESHOLD_MASK; in gen11_dsi_configure_transcoder()
658 tmp |= PIX_BUF_THRESHOLD_1_4; in gen11_dsi_configure_transcoder()
661 tmp &= ~PIX_VIRT_CHAN_MASK; in gen11_dsi_configure_transcoder()
662 tmp |= PIX_VIRT_CHAN(0); in gen11_dsi_configure_transcoder()
666 tmp |= BGR_TRANSMISSION; in gen11_dsi_configure_transcoder()
669 tmp &= ~PIX_FMT_MASK; in gen11_dsi_configure_transcoder()
675 tmp |= PIX_FMT_RGB565; in gen11_dsi_configure_transcoder()
678 tmp |= PIX_FMT_RGB666_PACKED; in gen11_dsi_configure_transcoder()
681 tmp |= PIX_FMT_RGB666_LOOSE; in gen11_dsi_configure_transcoder()
684 tmp |= PIX_FMT_RGB888; in gen11_dsi_configure_transcoder()
690 tmp |= BLANKING_PACKET_ENABLE; in gen11_dsi_configure_transcoder()
695 tmp &= ~OP_MODE_MASK; in gen11_dsi_configure_transcoder()
701 tmp |= VIDEO_MODE_SYNC_EVENT; in gen11_dsi_configure_transcoder()
704 tmp |= VIDEO_MODE_SYNC_PULSE; in gen11_dsi_configure_transcoder()
709 I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp); in gen11_dsi_configure_transcoder()
716 tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans)); in gen11_dsi_configure_transcoder()
717 tmp |= PORT_SYNC_MODE_ENABLE; in gen11_dsi_configure_transcoder()
718 I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); in gen11_dsi_configure_transcoder()
729 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); in gen11_dsi_configure_transcoder()
730 tmp &= ~DDI_PORT_WIDTH_MASK; in gen11_dsi_configure_transcoder()
731 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); in gen11_dsi_configure_transcoder()
734 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; in gen11_dsi_configure_transcoder()
740 tmp |= TRANS_DDI_EDP_INPUT_A_ON; in gen11_dsi_configure_transcoder()
743 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; in gen11_dsi_configure_transcoder()
746 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; in gen11_dsi_configure_transcoder()
751 tmp |= TRANS_DDI_FUNC_ENABLE; in gen11_dsi_configure_transcoder()
752 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp); in gen11_dsi_configure_transcoder()
892 u32 tmp; in gen11_dsi_enable_transcoder() local
896 tmp = I915_READ(PIPECONF(dsi_trans)); in gen11_dsi_enable_transcoder()
897 tmp |= PIPECONF_ENABLE; in gen11_dsi_enable_transcoder()
898 I915_WRITE(PIPECONF(dsi_trans), tmp); in gen11_dsi_enable_transcoder()
913 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; in gen11_dsi_setup_timeouts() local
933 tmp = I915_READ(DSI_HSTX_TO(dsi_trans)); in gen11_dsi_setup_timeouts()
934 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; in gen11_dsi_setup_timeouts()
935 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); in gen11_dsi_setup_timeouts()
936 I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp); in gen11_dsi_setup_timeouts()
941 tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans)); in gen11_dsi_setup_timeouts()
942 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; in gen11_dsi_setup_timeouts()
943 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); in gen11_dsi_setup_timeouts()
944 I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp); in gen11_dsi_setup_timeouts()
949 tmp = I915_READ(DSI_TA_TO(dsi_trans)); in gen11_dsi_setup_timeouts()
950 tmp &= ~TA_TIMEOUT_VALUE_MASK; in gen11_dsi_setup_timeouts()
951 tmp |= TA_TIMEOUT_VALUE(ta_timeout); in gen11_dsi_setup_timeouts()
952 I915_WRITE(DSI_TA_TO(dsi_trans), tmp); in gen11_dsi_setup_timeouts()
995 u32 tmp; in gen11_dsi_powerup_panel() local
1006 tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans)); in gen11_dsi_powerup_panel()
1007 tmp &= NUMBER_RX_PLOAD_DW_MASK; in gen11_dsi_powerup_panel()
1009 tmp = tmp * 4; in gen11_dsi_powerup_panel()
1011 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); in gen11_dsi_powerup_panel()
1013 DRM_ERROR("error setting max return pkt size%d\n", tmp); in gen11_dsi_powerup_panel()
1070 u32 tmp; in gen11_dsi_disable_transcoder() local
1076 tmp = I915_READ(PIPECONF(dsi_trans)); in gen11_dsi_disable_transcoder()
1077 tmp &= ~PIPECONF_ENABLE; in gen11_dsi_disable_transcoder()
1078 I915_WRITE(PIPECONF(dsi_trans), tmp); in gen11_dsi_disable_transcoder()
1105 u32 tmp; in gen11_dsi_deconfigure_trancoder() local
1110 tmp = I915_READ(DSI_LP_MSG(dsi_trans)); in gen11_dsi_deconfigure_trancoder()
1111 tmp |= LINK_ENTER_ULPS; in gen11_dsi_deconfigure_trancoder()
1112 tmp &= ~LINK_ULPS_TYPE_LP11; in gen11_dsi_deconfigure_trancoder()
1113 I915_WRITE(DSI_LP_MSG(dsi_trans), tmp); in gen11_dsi_deconfigure_trancoder()
1124 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); in gen11_dsi_deconfigure_trancoder()
1125 tmp &= ~TRANS_DDI_FUNC_ENABLE; in gen11_dsi_deconfigure_trancoder()
1126 I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp); in gen11_dsi_deconfigure_trancoder()
1133 tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans)); in gen11_dsi_deconfigure_trancoder()
1134 tmp &= ~PORT_SYNC_MODE_ENABLE; in gen11_dsi_deconfigure_trancoder()
1135 I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); in gen11_dsi_deconfigure_trancoder()
1144 u32 tmp; in gen11_dsi_disable_port() local
1149 tmp = I915_READ(DDI_BUF_CTL(port)); in gen11_dsi_disable_port()
1150 tmp &= ~DDI_BUF_CTL_ENABLE; in gen11_dsi_disable_port()
1151 I915_WRITE(DDI_BUF_CTL(port), tmp); in gen11_dsi_disable_port()
1167 u32 tmp; in gen11_dsi_disable_io_power() local
1182 tmp = I915_READ(ICL_DSI_IO_MODECTL(port)); in gen11_dsi_disable_io_power()
1183 tmp &= ~COMBO_PHY_MODE_DSI; in gen11_dsi_disable_io_power()
1184 I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp); in gen11_dsi_disable_io_power()
1308 u32 tmp; in gen11_dsi_get_hw_state() local
1317 tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); in gen11_dsi_get_hw_state()
1318 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { in gen11_dsi_get_hw_state()
1333 tmp = I915_READ(PIPECONF(dsi_trans)); in gen11_dsi_get_hw_state()
1334 ret = tmp & PIPECONF_ENABLE; in gen11_dsi_get_hw_state()