470 	OUT_RING(GFX_OP_COLOR_FACTOR);  in i810EmitContextVerified()
471 	OUT_RING(code[I810_CTXREG_CF1]);  in i810EmitContextVerified()
473 	OUT_RING(GFX_OP_STIPPLE);  in i810EmitContextVerified()
474 	OUT_RING(code[I810_CTXREG_ST1]);  in i810EmitContextVerified()
481 			OUT_RING(tmp);  in i810EmitContextVerified()
488 		OUT_RING(0);  in i810EmitContextVerified()
502 	OUT_RING(GFX_OP_MAP_INFO);  in i810EmitTexVerified()
503 	OUT_RING(code[I810_TEXREG_MI1]);  in i810EmitTexVerified()
504 	OUT_RING(code[I810_TEXREG_MI2]);  in i810EmitTexVerified()
505 	OUT_RING(code[I810_TEXREG_MI3]);  in i810EmitTexVerified()
512 			OUT_RING(tmp);  in i810EmitTexVerified()
519 		OUT_RING(0);  in i810EmitTexVerified()
537 		OUT_RING(CMD_OP_DESTBUFFER_INFO);  in i810EmitDestVerified()
538 		OUT_RING(tmp);  in i810EmitDestVerified()
545 	OUT_RING(CMD_OP_Z_BUFFER_INFO);  in i810EmitDestVerified()
546 	OUT_RING(dev_priv->zi1);  in i810EmitDestVerified()
548 	OUT_RING(GFX_OP_DESTBUFFER_VARS);  in i810EmitDestVerified()
549 	OUT_RING(code[I810_DESTREG_DV1]);  in i810EmitDestVerified()
551 	OUT_RING(GFX_OP_DRAWRECT_INFO);  in i810EmitDestVerified()
552 	OUT_RING(code[I810_DESTREG_DR1]);  in i810EmitDestVerified()
553 	OUT_RING(code[I810_DESTREG_DR2]);  in i810EmitDestVerified()
554 	OUT_RING(code[I810_DESTREG_DR3]);  in i810EmitDestVerified()
555 	OUT_RING(code[I810_DESTREG_DR4]);  in i810EmitDestVerified()
556 	OUT_RING(0);  in i810EmitDestVerified()
634 			OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);  in i810_dma_dispatch_clear()
635 			OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);  in i810_dma_dispatch_clear()
636 			OUT_RING((height << 16) | width);  in i810_dma_dispatch_clear()
637 			OUT_RING(start);  in i810_dma_dispatch_clear()
638 			OUT_RING(clear_color);  in i810_dma_dispatch_clear()
639 			OUT_RING(0);  in i810_dma_dispatch_clear()
645 			OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);  in i810_dma_dispatch_clear()
646 			OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);  in i810_dma_dispatch_clear()
647 			OUT_RING((height << 16) | width);  in i810_dma_dispatch_clear()
648 			OUT_RING(dev_priv->back_offset + start);  in i810_dma_dispatch_clear()
649 			OUT_RING(clear_color);  in i810_dma_dispatch_clear()
650 			OUT_RING(0);  in i810_dma_dispatch_clear()
656 			OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);  in i810_dma_dispatch_clear()
657 			OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);  in i810_dma_dispatch_clear()
658 			OUT_RING((height << 16) | width);  in i810_dma_dispatch_clear()
659 			OUT_RING(dev_priv->depth_offset + start);  in i810_dma_dispatch_clear()
660 			OUT_RING(clear_zval);  in i810_dma_dispatch_clear()
661 			OUT_RING(0);  in i810_dma_dispatch_clear()
697 		OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);  in i810_dma_dispatch_swap()
698 		OUT_RING(pitch | (0xCC << 16));  in i810_dma_dispatch_swap()
699 		OUT_RING((h << 16) | (w * cpp));  in i810_dma_dispatch_swap()
701 			OUT_RING(dev_priv->front_offset + start);  in i810_dma_dispatch_swap()
703 			OUT_RING(dev_priv->back_offset + start);  in i810_dma_dispatch_swap()
704 		OUT_RING(pitch);  in i810_dma_dispatch_swap()
706 			OUT_RING(dev_priv->back_offset + start);  in i810_dma_dispatch_swap()
708 			OUT_RING(dev_priv->front_offset + start);  in i810_dma_dispatch_swap()
755 				OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |  in i810_dma_dispatch_vertex()
757 				OUT_RING(GFX_OP_SCISSOR_INFO);  in i810_dma_dispatch_vertex()
758 				OUT_RING(box[i].x1 | (box[i].y1 << 16));  in i810_dma_dispatch_vertex()
759 				OUT_RING((box[i].x2 -  in i810_dma_dispatch_vertex()
765 			OUT_RING(CMD_OP_BATCH_BUFFER);  in i810_dma_dispatch_vertex()
766 			OUT_RING(start | BB1_PROTECTED);  in i810_dma_dispatch_vertex()
767 			OUT_RING(start + used - 4);  in i810_dma_dispatch_vertex()
768 			OUT_RING(0);  in i810_dma_dispatch_vertex()
781 		OUT_RING(CMD_STORE_DWORD_IDX);  in i810_dma_dispatch_vertex()
782 		OUT_RING(20);  in i810_dma_dispatch_vertex()
783 		OUT_RING(dev_priv->counter);  in i810_dma_dispatch_vertex()
784 		OUT_RING(CMD_STORE_DWORD_IDX);  in i810_dma_dispatch_vertex()
785 		OUT_RING(buf_priv->my_use_idx);  in i810_dma_dispatch_vertex()
786 		OUT_RING(I810_BUF_FREE);  in i810_dma_dispatch_vertex()
787 		OUT_RING(CMD_REPORT_HEAD);  in i810_dma_dispatch_vertex()
788 		OUT_RING(0);  in i810_dma_dispatch_vertex()
806 	OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);  in i810_dma_dispatch_flip()
807 	OUT_RING(0);  in i810_dma_dispatch_flip()
815 	OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );  in i810_dma_dispatch_flip()
817 		OUT_RING(dev_priv->back_offset);  in i810_dma_dispatch_flip()
820 		OUT_RING(dev_priv->front_offset);  in i810_dma_dispatch_flip()
823 	OUT_RING(0);  in i810_dma_dispatch_flip()
827 	OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);  in i810_dma_dispatch_flip()
828 	OUT_RING(0);  in i810_dma_dispatch_flip()
847 	OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);  in i810_dma_quiescent()
848 	OUT_RING(CMD_REPORT_HEAD);  in i810_dma_quiescent()
849 	OUT_RING(0);  in i810_dma_quiescent()
850 	OUT_RING(0);  in i810_dma_quiescent()
866 	OUT_RING(CMD_REPORT_HEAD);  in i810_flush_queue()
867 	OUT_RING(0);  in i810_flush_queue()
1073 	OUT_RING(CMD_OP_BATCH_BUFFER);  in i810_dma_dispatch_mc()
1074 	OUT_RING(start | BB1_PROTECTED);  in i810_dma_dispatch_mc()
1075 	OUT_RING(start + used - 4);  in i810_dma_dispatch_mc()
1076 	OUT_RING(0);  in i810_dma_dispatch_mc()
1080 	OUT_RING(CMD_STORE_DWORD_IDX);  in i810_dma_dispatch_mc()
1081 	OUT_RING(buf_priv->my_use_idx);  in i810_dma_dispatch_mc()
1082 	OUT_RING(I810_BUF_FREE);  in i810_dma_dispatch_mc()
1083 	OUT_RING(0);  in i810_dma_dispatch_mc()
1085 	OUT_RING(CMD_STORE_DWORD_IDX);  in i810_dma_dispatch_mc()
1086 	OUT_RING(16);  in i810_dma_dispatch_mc()
1087 	OUT_RING(last_render);  in i810_dma_dispatch_mc()
1088 	OUT_RING(0);  in i810_dma_dispatch_mc()