648 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)  in reg_write()  function
692 		reg_write(priv, reg, old_val | val);  in reg_set()
702 		reg_write(priv, reg, old_val & ~val);  in reg_clear()
709 	reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);  in tda998x_reset()
711 	reg_write(priv, REG_SOFTRESET, 0);  in tda998x_reset()
719 	reg_write(priv, REG_PLL_SERIAL_1, 0x00);  in tda998x_reset()
720 	reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));  in tda998x_reset()
721 	reg_write(priv, REG_PLL_SERIAL_3, 0x00);  in tda998x_reset()
722 	reg_write(priv, REG_SERIALIZER,   0x00);  in tda998x_reset()
723 	reg_write(priv, REG_BUFFER_OUT,   0x00);  in tda998x_reset()
724 	reg_write(priv, REG_PLL_SCG1,     0x00);  in tda998x_reset()
725 	reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);  in tda998x_reset()
726 	reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);  in tda998x_reset()
727 	reg_write(priv, REG_PLL_SCGN1,    0xfa);  in tda998x_reset()
728 	reg_write(priv, REG_PLL_SCGN2,    0x00);  in tda998x_reset()
729 	reg_write(priv, REG_PLL_SCGR1,    0x5b);  in tda998x_reset()
730 	reg_write(priv, REG_PLL_SCGR2,    0x00);  in tda998x_reset()
731 	reg_write(priv, REG_PLL_SCG2,     0x10);  in tda998x_reset()
734 	reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);  in tda998x_reset()
1014 	reg_write(priv, REG_ENA_AP, settings->ena_ap);  in tda998x_configure_audio()
1015 	reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk);  in tda998x_configure_audio()
1016 	reg_write(priv, REG_MUX_AP, settings->route->mux_ap);  in tda998x_configure_audio()
1017 	reg_write(priv, REG_I2S_FORMAT, settings->i2s_format);  in tda998x_configure_audio()
1018 	reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel);  in tda998x_configure_audio()
1021 	reg_write(priv, REG_CTS_N, settings->cts_n);  in tda998x_configure_audio()
1022 	reg_write(priv, REG_AUDIO_DIV, adiv);  in tda998x_configure_audio()
1128 	reg_write(priv, REG_ENA_AP, 0);  in tda998x_audio_shutdown()
1223 	reg_write(priv, REG_DDC_ADDR, 0xa0);  in read_edid_block()
1224 	reg_write(priv, REG_DDC_OFFS, offset);  in read_edid_block()
1225 	reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);  in read_edid_block()
1226 	reg_write(priv, REG_DDC_SEGM, segptr);  in read_edid_block()
1230 	reg_write(priv, REG_EDID_CTRL, 0x1);  in read_edid_block()
1233 	reg_write(priv, REG_EDID_CTRL, 0x0);  in read_edid_block()
1393 		reg_write(priv, REG_ENA_VP_0, 0xff);  in tda998x_bridge_enable()
1394 		reg_write(priv, REG_ENA_VP_1, 0xff);  in tda998x_bridge_enable()
1395 		reg_write(priv, REG_ENA_VP_2, 0xff);  in tda998x_bridge_enable()
1397 		reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);  in tda998x_bridge_enable()
1398 		reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);  in tda998x_bridge_enable()
1399 		reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);  in tda998x_bridge_enable()
1411 		reg_write(priv, REG_ENA_VP_0, 0x00);  in tda998x_bridge_disable()
1412 		reg_write(priv, REG_ENA_VP_1, 0x00);  in tda998x_bridge_disable()
1413 		reg_write(priv, REG_ENA_VP_2, 0x00);  in tda998x_bridge_disable()
1536 	reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);  in tda998x_bridge_mode_set()
1538 	reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));  in tda998x_bridge_mode_set()
1541 	reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |  in tda998x_bridge_mode_set()
1544 	reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));  in tda998x_bridge_mode_set()
1545 	reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |  in tda998x_bridge_mode_set()
1551 	reg_write(priv, REG_SERIALIZER, 0);  in tda998x_bridge_mode_set()
1552 	reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));  in tda998x_bridge_mode_set()
1554 	reg_write(priv, REG_RPT_CNTRL, RPT_CNTRL_REPEAT(rep));  in tda998x_bridge_mode_set()
1555 	reg_write(priv, REG_SEL_CLK, sel_clk);  in tda998x_bridge_mode_set()
1556 	reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |  in tda998x_bridge_mode_set()
1574 		reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |  in tda998x_bridge_mode_set()
1580 	reg_write(priv, REG_ANA_GENERAL, 0x09);  in tda998x_bridge_mode_set()
1595 	reg_write(priv, REG_VIP_CNTRL_3, reg);  in tda998x_bridge_mode_set()
1597 	reg_write(priv, REG_VIDFORMAT, 0x00);  in tda998x_bridge_mode_set()
1621 		reg_write(priv, REG_ENABLE_SPACE, 0x00);  in tda998x_bridge_mode_set()
1633 	reg_write(priv, REG_TBG_CNTRL_1, reg);  in tda998x_bridge_mode_set()
1636 	reg_write(priv, REG_TBG_CNTRL_0, 0);  in tda998x_bridge_mode_set()
1654 		reg_write(priv, REG_TBG_CNTRL_1, reg);  in tda998x_bridge_mode_set()
1655 		reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));  in tda998x_bridge_mode_set()
1872 	reg_write(priv, REG_DDC_DISABLE, 0x00);  in tda998x_create()
1875 	reg_write(priv, REG_TX3, 39);  in tda998x_create()