658 			      struct drm_display_mode *adjusted_mode,  in mdfld_crtc_mode_set()  argument
688 		android_hdmi_crtc_mode_set(crtc, mode, adjusted_mode,  in mdfld_crtc_mode_set()
699 		 adjusted_mode->hdisplay);  in mdfld_crtc_mode_set()
701 		 adjusted_mode->vdisplay);  in mdfld_crtc_mode_set()
703 		 adjusted_mode->hsync_start);  in mdfld_crtc_mode_set()
705 		 adjusted_mode->hsync_end);  in mdfld_crtc_mode_set()
707 		 adjusted_mode->htotal);  in mdfld_crtc_mode_set()
709 		 adjusted_mode->vsync_start);  in mdfld_crtc_mode_set()
711 		 adjusted_mode->vsync_end);  in mdfld_crtc_mode_set()
713 		 adjusted_mode->vtotal);  in mdfld_crtc_mode_set()
715 		 adjusted_mode->clock);  in mdfld_crtc_mode_set()
726 	memcpy(&gma_crtc->saved_adjusted_mode, adjusted_mode,  in mdfld_crtc_mode_set()
774 		REG_WRITE(map->size, ((min(mode->crtc_vdisplay, adjusted_mode->crtc_vdisplay) - 1) << 16)  in mdfld_crtc_mode_set()
775 				| (min(mode->crtc_hdisplay, adjusted_mode->crtc_hdisplay) - 1));  in mdfld_crtc_mode_set()
801 		offsetX = (adjusted_mode->crtc_hdisplay -  in mdfld_crtc_mode_set()
803 		offsetY = (adjusted_mode->crtc_vdisplay -  in mdfld_crtc_mode_set()
807 			((adjusted_mode->crtc_htotal - 1) << 16));  in mdfld_crtc_mode_set()
809 			((adjusted_mode->crtc_vtotal - 1) << 16));  in mdfld_crtc_mode_set()
810 		REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start -  in mdfld_crtc_mode_set()
812 			((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16));  in mdfld_crtc_mode_set()
813 		REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start -  in mdfld_crtc_mode_set()
815 			((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16));  in mdfld_crtc_mode_set()
816 		REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start -  in mdfld_crtc_mode_set()
818 			((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16));  in mdfld_crtc_mode_set()
819 		REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start -  in mdfld_crtc_mode_set()
821 			((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16));  in mdfld_crtc_mode_set()
823 		REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |  in mdfld_crtc_mode_set()
824 			((adjusted_mode->crtc_htotal - 1) << 16));  in mdfld_crtc_mode_set()
825 		REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |  in mdfld_crtc_mode_set()
826 			((adjusted_mode->crtc_vtotal - 1) << 16));  in mdfld_crtc_mode_set()
827 		REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |  in mdfld_crtc_mode_set()
828 			((adjusted_mode->crtc_hblank_end - 1) << 16));  in mdfld_crtc_mode_set()
829 		REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |  in mdfld_crtc_mode_set()
830 			((adjusted_mode->crtc_hsync_end - 1) << 16));  in mdfld_crtc_mode_set()
831 		REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |  in mdfld_crtc_mode_set()
832 			((adjusted_mode->crtc_vblank_end - 1) << 16));  in mdfld_crtc_mode_set()
833 		REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |  in mdfld_crtc_mode_set()
834 			((adjusted_mode->crtc_vsync_end - 1) << 16));  in mdfld_crtc_mode_set()
854 	clk = adjusted_mode->clock;  in mdfld_crtc_mode_set()
899 					adjusted_mode->clock, clk_tmp);  in mdfld_crtc_mode_set()