83 	REG_WRITE(map->stride, fb->pitches[0]);  in gma_pipe_set_base()
107 	REG_WRITE(map->cntr, dspcntr);  in gma_pipe_set_base()
116 		REG_WRITE(map->base, offset + start);  in gma_pipe_set_base()
119 		REG_WRITE(map->base, offset);  in gma_pipe_set_base()
121 		REG_WRITE(map->surf, start);  in gma_pipe_set_base()
156 			REG_WRITE(palreg + 4 * i,  in gma_crtc_load_lut()
217 			REG_WRITE(map->dpll, temp);  in gma_crtc_dpms()
221 			REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);  in gma_crtc_dpms()
225 			REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);  in gma_crtc_dpms()
234 			REG_WRITE(map->cntr,  in gma_crtc_dpms()
237 			REG_WRITE(map->base, REG_READ(map->base));  in gma_crtc_dpms()
245 			REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);  in gma_crtc_dpms()
250 		REG_WRITE(map->status, temp);  in gma_crtc_dpms()
270 		REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);  in gma_crtc_dpms()
281 			REG_WRITE(map->cntr,  in gma_crtc_dpms()
284 			REG_WRITE(map->base, REG_READ(map->base));  in gma_crtc_dpms()
291 			REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);  in gma_crtc_dpms()
303 			REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);  in gma_crtc_dpms()
316 	REG_WRITE(DSPARB, 0x3F3E);  in gma_crtc_dpms()
342 			REG_WRITE(control, temp);  in gma_crtc_cursor_set()
343 			REG_WRITE(base, 0);  in gma_crtc_cursor_set()
419 		REG_WRITE(control, temp);  in gma_crtc_cursor_set()
420 		REG_WRITE(base, addr);  in gma_crtc_cursor_set()
463 		REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);  in gma_crtc_cursor_move()
464 		REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);  in gma_crtc_cursor_move()
583 		REG_WRITE(map->dpll,  in gma_crtc_restore()
589 	REG_WRITE(map->fp0, crtc_state->saveFP0);  in gma_crtc_restore()
592 	REG_WRITE(map->fp1, crtc_state->saveFP1);  in gma_crtc_restore()
595 	REG_WRITE(map->dpll, crtc_state->saveDPLL);  in gma_crtc_restore()
599 	REG_WRITE(map->htotal, crtc_state->saveHTOTAL);  in gma_crtc_restore()
600 	REG_WRITE(map->hblank, crtc_state->saveHBLANK);  in gma_crtc_restore()
601 	REG_WRITE(map->hsync, crtc_state->saveHSYNC);  in gma_crtc_restore()
602 	REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);  in gma_crtc_restore()
603 	REG_WRITE(map->vblank, crtc_state->saveVBLANK);  in gma_crtc_restore()
604 	REG_WRITE(map->vsync, crtc_state->saveVSYNC);  in gma_crtc_restore()
605 	REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);  in gma_crtc_restore()
607 	REG_WRITE(map->size, crtc_state->saveDSPSIZE);  in gma_crtc_restore()
608 	REG_WRITE(map->pos, crtc_state->saveDSPPOS);  in gma_crtc_restore()
610 	REG_WRITE(map->src, crtc_state->savePIPESRC);  in gma_crtc_restore()
611 	REG_WRITE(map->base, crtc_state->saveDSPBASE);  in gma_crtc_restore()
612 	REG_WRITE(map->conf, crtc_state->savePIPECONF);  in gma_crtc_restore()
616 	REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);  in gma_crtc_restore()
617 	REG_WRITE(map->base, crtc_state->saveDSPBASE);  in gma_crtc_restore()
623 		REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]);  in gma_crtc_restore()