Lines Matching refs:timing_base
96 unsigned int timing_base; member
115 .timing_base = 0x0,
121 .timing_base = 0x0,
127 .timing_base = 0x20000,
135 .timing_base = 0x0,
144 .timing_base = 0x20000,
155 .timing_base = 0x20000,
435 void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base; in fimd_setup_trigger() local
437 u32 val = readl(timing_base + TRIGCON); in fimd_setup_trigger()
450 writel(val, timing_base + TRIGCON); in fimd_setup_trigger()
458 void *timing_base = ctx->regs + driver_data->timing_base; in fimd_commit() local
470 writel(val, timing_base + I80IFCONFAx(0)); in fimd_commit()
473 writel(0, timing_base + I80IFCONFBx(0)); in fimd_commit()
495 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); in fimd_commit()
505 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); in fimd_commit()
515 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); in fimd_commit()
519 writel(ctx->vidout_con, timing_base + VIDOUT_CON); in fimd_commit()
549 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); in fimd_commit()
945 void *timing_base = ctx->regs + driver_data->timing_base; in fimd_trigger() local
958 reg = readl(timing_base + TRIGCON); in fimd_trigger()
960 writel(reg, timing_base + TRIGCON); in fimd_trigger()