283 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)  in dsi_write()  function
368 	dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);  in dw_mipi_message_config()
369 	dsi_write(dsi, DSI_CMD_MODE_CFG, val);  in dw_mipi_message_config()
385 	dsi_write(dsi, DSI_GEN_HDR, hdr_val);  in dw_mipi_dsi_gen_pkt_hdr_write()
411 			dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));  in dw_mipi_dsi_write()
415 			dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));  in dw_mipi_dsi_write()
538 	dsi_write(dsi, DSI_VID_MODE_CFG, val);  in dw_mipi_dsi_video_mode_config()
544 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_set_mode()
547 		dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);  in dw_mipi_dsi_set_mode()
549 		dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);  in dw_mipi_dsi_set_mode()
551 		dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);  in dw_mipi_dsi_set_mode()
554 	dsi_write(dsi, DSI_PWR_UP, POWERUP);  in dw_mipi_dsi_set_mode()
559 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_disable()
560 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);  in dw_mipi_dsi_disable()
575 	dsi_write(dsi, DSI_PWR_UP, RESET);  in dw_mipi_dsi_init()
582 	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |  in dw_mipi_dsi_init()
611 	dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));  in dw_mipi_dsi_dpi_config()
612 	dsi_write(dsi, DSI_DPI_COLOR_CODING, color);  in dw_mipi_dsi_dpi_config()
613 	dsi_write(dsi, DSI_DPI_CFG_POL, val);  in dw_mipi_dsi_dpi_config()
620 	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)  in dw_mipi_dsi_dpi_config()
626 	dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);  in dw_mipi_dsi_packet_handler_config()
640 	dsi_write(dsi, DSI_VID_PKT_SIZE,  in dw_mipi_dsi_video_packet_config()
653 	dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));  in dw_mipi_dsi_command_mode_config()
659 	dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);  in dw_mipi_dsi_command_mode_config()
660 	dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);  in dw_mipi_dsi_command_mode_config()
694 	dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
697 	dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
700 	dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);  in dw_mipi_dsi_line_timer_config()
713 	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);  in dw_mipi_dsi_vertical_timing_config()
714 	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);  in dw_mipi_dsi_vertical_timing_config()
715 	dsi_write(dsi, DSI_VID_VFP_LINES, vfp);  in dw_mipi_dsi_vertical_timing_config()
716 	dsi_write(dsi, DSI_VID_VBP_LINES, vbp);  in dw_mipi_dsi_vertical_timing_config()
734 		dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |  in dw_mipi_dsi_dphy_timing_config()
736 		dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));  in dw_mipi_dsi_dphy_timing_config()
738 		dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |  in dw_mipi_dsi_dphy_timing_config()
742 	dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)  in dw_mipi_dsi_dphy_timing_config()
753 	dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |  in dw_mipi_dsi_dphy_interface_config()
760 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK  in dw_mipi_dsi_dphy_init()
762 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);  in dw_mipi_dsi_dphy_init()
763 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);  in dw_mipi_dsi_dphy_init()
764 	dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);  in dw_mipi_dsi_dphy_init()
772 	dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |  in dw_mipi_dsi_dphy_enable()
791 	dsi_write(dsi, DSI_INT_MSK0, 0);  in dw_mipi_dsi_clear_err()
792 	dsi_write(dsi, DSI_INT_MSK1, 0);  in dw_mipi_dsi_clear_err()