Lines Matching full:table
420 pr_err("vdd_dep_on_sclk table is NULL\n"); in ci_populate_single_graphic_level()
584 "The CAC Leakage table does not exist!", return -EINVAL); in ci_populate_bapm_vddc_vid_sidd()
772 "The SCLK/VDDC Dependency Table does not exist.\n", in ci_get_std_voltage_value_sidd()
776 pr_warn("CAC Leakage Table does not exist, using vddc.\n"); in ci_get_std_voltage_value_sidd()
787 …warn("Index from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index, using maximum ind… in ci_get_std_voltage_value_sidd()
803 …ex from SCLK/VDDC Dependency Table exceeds the CAC Leakage Table index in second look up, using ma… in ci_get_std_voltage_value_sidd()
812 pr_warn("Unable to get std_vddc from SCLK/VDDC Dependency Table, using vddc.\n"); in ci_get_std_voltage_value_sidd()
840 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vddc_table() argument
846 table->VddcLevelCount = data->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
847 for (count = 0; count < table->VddcLevelCount; count++) { in ci_populate_smc_vddc_table()
850 &(table->VddcLevel[count])); in ci_populate_smc_vddc_table()
851 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL); in ci_populate_smc_vddc_table()
855 table->VddcLevel[count].Smio = (uint8_t) count; in ci_populate_smc_vddc_table()
856 table->Smio[count] |= data->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
857 table->SmioMaskVddcVid |= data->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
859 table->VddcLevel[count].Smio = 0; in ci_populate_smc_vddc_table()
863 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount); in ci_populate_smc_vddc_table()
869 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vdd_ci_table() argument
875 table->VddciLevelCount = data->vddci_voltage_table.count; in ci_populate_smc_vdd_ci_table()
877 for (count = 0; count < table->VddciLevelCount; count++) { in ci_populate_smc_vdd_ci_table()
880 &(table->VddciLevel[count])); in ci_populate_smc_vdd_ci_table()
881 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL); in ci_populate_smc_vdd_ci_table()
883 table->VddciLevel[count].Smio = (uint8_t) count; in ci_populate_smc_vdd_ci_table()
884 table->Smio[count] |= data->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vdd_ci_table()
885 table->SmioMaskVddciVid |= data->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vdd_ci_table()
887 table->VddciLevel[count].Smio = 0; in ci_populate_smc_vdd_ci_table()
891 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount); in ci_populate_smc_vdd_ci_table()
897 SMU7_Discrete_DpmTable *table) in ci_populate_smc_mvdd_table() argument
903 table->MvddLevelCount = data->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
905 for (count = 0; count < table->MvddLevelCount; count++) { in ci_populate_smc_mvdd_table()
908 &table->MvddLevel[count]); in ci_populate_smc_mvdd_table()
909 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL); in ci_populate_smc_mvdd_table()
911 table->MvddLevel[count].Smio = (uint8_t) count; in ci_populate_smc_mvdd_table()
912 table->Smio[count] |= data->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
913 table->SmioMaskMvddVid |= data->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
915 table->MvddLevel[count].Smio = 0; in ci_populate_smc_mvdd_table()
919 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount); in ci_populate_smc_mvdd_table()
926 SMU7_Discrete_DpmTable *table) in ci_populate_smc_voltage_tables() argument
930 result = ci_populate_smc_vddc_table(hwmgr, table); in ci_populate_smc_voltage_tables()
932 "can not populate VDDC voltage table to SMC", return -EINVAL); in ci_populate_smc_voltage_tables()
934 result = ci_populate_smc_vdd_ci_table(hwmgr, table); in ci_populate_smc_voltage_tables()
936 "can not populate VDDCI voltage table to SMC", return -EINVAL); in ci_populate_smc_voltage_tables()
938 result = ci_populate_smc_mvdd_table(hwmgr, table); in ci_populate_smc_voltage_tables()
940 "can not populate MVDD voltage table to SMC", return -EINVAL); in ci_populate_smc_voltage_tables()
995 static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table) in ci_populate_smc_link_level() argument
1004 table->LinkLevel[i].PcieGenSpeed = in ci_populate_smc_link_level()
1006 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
1008 table->LinkLevel[i].EnabledForActivity = 1; in ci_populate_smc_link_level()
1009 table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5); in ci_populate_smc_link_level()
1010 table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30); in ci_populate_smc_link_level()
1189 "can not find MinVddc voltage value from memory VDDC voltage dependency table", return result); in ci_populate_single_memory_level()
1198 "can not find MinVddci voltage value from memory VDDCI voltage dependency table", return result); in ci_populate_single_memory_level()
1207 "can not find MinVddci voltage value from memory MVDD voltage dependency table", return result); in ci_populate_single_memory_level()
1376 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acpi_level() argument
1390 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; in ci_populate_smc_acpi_level()
1393 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
1395 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
1397 table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
1399 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); in ci_populate_smc_acpi_level()
1403 table->ACPILevel.SclkFrequency, ÷rs); in ci_populate_smc_acpi_level()
1409 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_acpi_level()
1410 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; in ci_populate_smc_acpi_level()
1411 table->ACPILevel.DeepSleepDivId = 0; in ci_populate_smc_acpi_level()
1420 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; in ci_populate_smc_acpi_level()
1421 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; in ci_populate_smc_acpi_level()
1422 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; in ci_populate_smc_acpi_level()
1423 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; in ci_populate_smc_acpi_level()
1424 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; in ci_populate_smc_acpi_level()
1425 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; in ci_populate_smc_acpi_level()
1426 table->ACPILevel.CcPwrDynRm = 0; in ci_populate_smc_acpi_level()
1427 table->ACPILevel.CcPwrDynRm1 = 0; in ci_populate_smc_acpi_level()
1430 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); in ci_populate_smc_acpi_level()
1432 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency); in ci_populate_smc_acpi_level()
1433 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl); in ci_populate_smc_acpi_level()
1434 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2); in ci_populate_smc_acpi_level()
1435 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3); in ci_populate_smc_acpi_level()
1436 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4); in ci_populate_smc_acpi_level()
1437 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum); in ci_populate_smc_acpi_level()
1438 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2); in ci_populate_smc_acpi_level()
1439 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); in ci_populate_smc_acpi_level()
1440 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); in ci_populate_smc_acpi_level()
1443 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/ in ci_populate_smc_acpi_level()
1444 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; in ci_populate_smc_acpi_level()
1445 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in ci_populate_smc_acpi_level()
1448 table->MemoryACPILevel.MinVddci = table->MemoryACPILevel.MinVddc; in ci_populate_smc_acpi_level()
1451 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
1453 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
1457 table->MemoryACPILevel.MinMvdd = in ci_populate_smc_acpi_level()
1460 table->MemoryACPILevel.MinMvdd = 0; in ci_populate_smc_acpi_level()
1480 table->MemoryACPILevel.DllCntl = in ci_populate_smc_acpi_level()
1482 table->MemoryACPILevel.MclkPwrmgtCntl = in ci_populate_smc_acpi_level()
1484 table->MemoryACPILevel.MpllAdFuncCntl = in ci_populate_smc_acpi_level()
1486 table->MemoryACPILevel.MpllDqFuncCntl = in ci_populate_smc_acpi_level()
1488 table->MemoryACPILevel.MpllFuncCntl = in ci_populate_smc_acpi_level()
1490 table->MemoryACPILevel.MpllFuncCntl_1 = in ci_populate_smc_acpi_level()
1492 table->MemoryACPILevel.MpllFuncCntl_2 = in ci_populate_smc_acpi_level()
1494 table->MemoryACPILevel.MpllSs1 = in ci_populate_smc_acpi_level()
1496 table->MemoryACPILevel.MpllSs2 = in ci_populate_smc_acpi_level()
1499 table->MemoryACPILevel.EnabledForThrottle = 0; in ci_populate_smc_acpi_level()
1500 table->MemoryACPILevel.EnabledForActivity = 0; in ci_populate_smc_acpi_level()
1501 table->MemoryACPILevel.UpH = 0; in ci_populate_smc_acpi_level()
1502 table->MemoryACPILevel.DownH = 100; in ci_populate_smc_acpi_level()
1503 table->MemoryACPILevel.VoltageDownH = 0; in ci_populate_smc_acpi_level()
1505 …table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activi… in ci_populate_smc_acpi_level()
1507 table->MemoryACPILevel.StutterEnable = 0; in ci_populate_smc_acpi_level()
1508 table->MemoryACPILevel.StrobeEnable = 0; in ci_populate_smc_acpi_level()
1509 table->MemoryACPILevel.EdcReadEnable = 0; in ci_populate_smc_acpi_level()
1510 table->MemoryACPILevel.EdcWriteEnable = 0; in ci_populate_smc_acpi_level()
1511 table->MemoryACPILevel.RttEnable = 0; in ci_populate_smc_acpi_level()
1517 SMU7_Discrete_DpmTable *table) in ci_populate_smc_uvd_level() argument
1525 table->UvdLevelCount = (uint8_t)(uvd_table->count); in ci_populate_smc_uvd_level()
1527 for (count = 0; count < table->UvdLevelCount; count++) { in ci_populate_smc_uvd_level()
1528 table->UvdLevel[count].VclkFrequency = in ci_populate_smc_uvd_level()
1530 table->UvdLevel[count].DclkFrequency = in ci_populate_smc_uvd_level()
1532 table->UvdLevel[count].MinVddc = in ci_populate_smc_uvd_level()
1534 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()
1537 table->UvdLevel[count].VclkFrequency, ÷rs); in ci_populate_smc_uvd_level()
1541 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_uvd_level()
1544 table->UvdLevel[count].DclkFrequency, ÷rs); in ci_populate_smc_uvd_level()
1548 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_uvd_level()
1549 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); in ci_populate_smc_uvd_level()
1550 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); in ci_populate_smc_uvd_level()
1551 CONVERT_FROM_HOST_TO_SMC_US(table->UvdLevel[count].MinVddc); in ci_populate_smc_uvd_level()
1558 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vce_level() argument
1566 table->VceLevelCount = (uint8_t)(vce_table->count); in ci_populate_smc_vce_level()
1567 table->VceBootLevel = 0; in ci_populate_smc_vce_level()
1569 for (count = 0; count < table->VceLevelCount; count++) { in ci_populate_smc_vce_level()
1570 table->VceLevel[count].Frequency = vce_table->entries[count].evclk; in ci_populate_smc_vce_level()
1571 table->VceLevel[count].MinVoltage = in ci_populate_smc_vce_level()
1573 table->VceLevel[count].MinPhases = 1; in ci_populate_smc_vce_level()
1576 table->VceLevel[count].Frequency, ÷rs); in ci_populate_smc_vce_level()
1581 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_vce_level()
1583 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); in ci_populate_smc_vce_level()
1584 CONVERT_FROM_HOST_TO_SMC_US(table->VceLevel[count].MinVoltage); in ci_populate_smc_vce_level()
1590 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acp_level() argument
1598 table->AcpLevelCount = (uint8_t)(acp_table->count); in ci_populate_smc_acp_level()
1599 table->AcpBootLevel = 0; in ci_populate_smc_acp_level()
1601 for (count = 0; count < table->AcpLevelCount; count++) { in ci_populate_smc_acp_level()
1602 table->AcpLevel[count].Frequency = acp_table->entries[count].acpclk; in ci_populate_smc_acp_level()
1603 table->AcpLevel[count].MinVoltage = acp_table->entries[count].v; in ci_populate_smc_acp_level()
1604 table->AcpLevel[count].MinPhases = 1; in ci_populate_smc_acp_level()
1607 table->AcpLevel[count].Frequency, ÷rs); in ci_populate_smc_acp_level()
1611 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; in ci_populate_smc_acp_level()
1613 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency); in ci_populate_smc_acp_level()
1614 CONVERT_FROM_HOST_TO_SMC_US(table->AcpLevel[count].MinVoltage); in ci_populate_smc_acp_level()
1684 SMU7_Discrete_DpmTable *table) in ci_populate_smc_boot_level() argument
1690 table->GraphicsBootLevel = 0; in ci_populate_smc_boot_level()
1691 table->MemoryBootLevel = 0; in ci_populate_smc_boot_level()
1693 /* find boot level from dpm table*/ in ci_populate_smc_boot_level()
1700 …pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0… in ci_populate_smc_boot_level()
1710 …pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\… in ci_populate_smc_boot_level()
1714 table->BootVddc = data->vbios_boot_state.vddc_bootup_value; in ci_populate_smc_boot_level()
1715 table->BootVddci = data->vbios_boot_state.vddci_bootup_value; in ci_populate_smc_boot_level()
1716 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value; in ci_populate_smc_boot_level()
1882 SMU7_Discrete_DpmTable *table) in ci_populate_smc_svi2_config() argument
1887 table->SVI2Enable = 1; in ci_populate_smc_svi2_config()
1889 table->SVI2Enable = 0; in ci_populate_smc_svi2_config()
1909 static int ci_populate_vr_config(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table) in ci_populate_vr_config() argument
1915 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT); in ci_populate_vr_config()
1919 table->VRConfig |= config; in ci_populate_vr_config()
1926 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT); in ci_populate_vr_config()
1929 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT); in ci_populate_vr_config()
1934 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT); in ci_populate_vr_config()
1945 SMU7_Discrete_DpmTable *table = &(smu_data->smc_state_table); in ci_init_smc_table() local
1953 ci_populate_smc_voltage_tables(hwmgr, table); in ci_init_smc_table()
1957 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; in ci_init_smc_table()
1962 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; in ci_init_smc_table()
1965 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; in ci_init_smc_table()
1968 result = ci_populate_ulv_state(hwmgr, &(table->Ulv)); in ci_init_smc_table()
1984 result = ci_populate_smc_link_level(hwmgr, table); in ci_init_smc_table()
1988 result = ci_populate_smc_acpi_level(hwmgr, table); in ci_init_smc_table()
1992 result = ci_populate_smc_vce_level(hwmgr, table); in ci_init_smc_table()
1996 result = ci_populate_smc_acp_level(hwmgr, table); in ci_init_smc_table()
2006 result = ci_populate_smc_uvd_level(hwmgr, table); in ci_init_smc_table()
2010 table->UvdBootLevel = 0; in ci_init_smc_table()
2011 table->VceBootLevel = 0; in ci_init_smc_table()
2012 table->AcpBootLevel = 0; in ci_init_smc_table()
2013 table->SamuBootLevel = 0; in ci_init_smc_table()
2015 table->GraphicsBootLevel = 0; in ci_init_smc_table()
2016 table->MemoryBootLevel = 0; in ci_init_smc_table()
2018 result = ci_populate_smc_boot_level(hwmgr, table); in ci_init_smc_table()
2028 table->UVDInterval = 1; in ci_init_smc_table()
2029 table->VCEInterval = 1; in ci_init_smc_table()
2030 table->ACPInterval = 1; in ci_init_smc_table()
2031 table->SAMUInterval = 1; in ci_init_smc_table()
2032 table->GraphicsVoltageChangeEnable = 1; in ci_init_smc_table()
2033 table->GraphicsThermThrottleEnable = 1; in ci_init_smc_table()
2034 table->GraphicsInterval = 1; in ci_init_smc_table()
2035 table->VoltageInterval = 1; in ci_init_smc_table()
2036 table->ThermalInterval = 1; in ci_init_smc_table()
2038 table->TemperatureLimitHigh = in ci_init_smc_table()
2041 table->TemperatureLimitLow = in ci_init_smc_table()
2045 table->MemoryVoltageChangeEnable = 1; in ci_init_smc_table()
2046 table->MemoryInterval = 1; in ci_init_smc_table()
2047 table->VoltageResponseTime = 0; in ci_init_smc_table()
2048 table->VddcVddciDelta = 4000; in ci_init_smc_table()
2049 table->PhaseResponseTime = 0; in ci_init_smc_table()
2050 table->MemoryThermThrottleEnable = 1; in ci_init_smc_table()
2056 table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count; in ci_init_smc_table()
2057 table->PCIeGenInterval = 1; in ci_init_smc_table()
2059 result = ci_populate_vr_config(hwmgr, table); in ci_init_smc_table()
2062 data->vr_config = table->VRConfig; in ci_init_smc_table()
2064 ci_populate_smc_svi2_config(hwmgr, table); in ci_init_smc_table()
2067 CONVERT_FROM_HOST_TO_SMC_UL(table->Smio[i]); in ci_init_smc_table()
2069 table->ThermGpio = 17; in ci_init_smc_table()
2070 table->SclkStepSize = 0x4000; in ci_init_smc_table()
2072 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift; in ci_init_smc_table()
2076 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN; in ci_init_smc_table()
2081 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN; in ci_init_smc_table()
2083 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); in ci_init_smc_table()
2084 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig); in ci_init_smc_table()
2085 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcVid); in ci_init_smc_table()
2086 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddcPhase); in ci_init_smc_table()
2087 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskVddciVid); in ci_init_smc_table()
2088 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMaskMvddVid); in ci_init_smc_table()
2089 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); in ci_init_smc_table()
2090 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); in ci_init_smc_table()
2091 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); in ci_init_smc_table()
2092 table->VddcVddciDelta = PP_HOST_TO_SMC_US(table->VddcVddciDelta); in ci_init_smc_table()
2093 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); in ci_init_smc_table()
2094 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); in ci_init_smc_table()
2096 table->BootVddc = PP_HOST_TO_SMC_US(table->BootVddc * VOLTAGE_SCALE); in ci_init_smc_table()
2097 table->BootVddci = PP_HOST_TO_SMC_US(table->BootVddci * VOLTAGE_SCALE); in ci_init_smc_table()
2098 table->BootMVdd = PP_HOST_TO_SMC_US(table->BootMVdd * VOLTAGE_SCALE); in ci_init_smc_table()
2103 (uint8_t *)&(table->SystemFlags), in ci_init_smc_table()
2112 "Failed to populate initialize MC Reg table!", return result); in ci_init_smc_table()
2237 PP_ASSERT_WITH_CODE((0 == result), "Failed to upload MC reg table!", return result); in ci_update_sclk_threshold()
2538 static int ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) in ci_set_s0_mc_reg_index() argument
2543 for (i = 0; i < table->last; i++) { in ci_set_s0_mc_reg_index()
2544 table->mc_reg_address[i].s0 = in ci_set_s0_mc_reg_index()
2545 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) in ci_set_s0_mc_reg_index()
2546 ? address : table->mc_reg_address[i].s1; in ci_set_s0_mc_reg_index()
2551 static int ci_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, in ci_copy_vbios_smc_reg_table() argument
2556 PP_ASSERT_WITH_CODE((table->last <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE), in ci_copy_vbios_smc_reg_table()
2557 "Invalid VramInfo table.", return -EINVAL); in ci_copy_vbios_smc_reg_table()
2558 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES), in ci_copy_vbios_smc_reg_table()
2559 "Invalid VramInfo table.", return -EINVAL); in ci_copy_vbios_smc_reg_table()
2561 for (i = 0; i < table->last; i++) in ci_copy_vbios_smc_reg_table()
2562 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in ci_copy_vbios_smc_reg_table()
2564 ni_table->last = table->last; in ci_copy_vbios_smc_reg_table()
2566 for (i = 0; i < table->num_entries; i++) { in ci_copy_vbios_smc_reg_table()
2568 table->mc_reg_table_entry[i].mclk_max; in ci_copy_vbios_smc_reg_table()
2569 for (j = 0; j < table->last; j++) { in ci_copy_vbios_smc_reg_table()
2571 table->mc_reg_table_entry[i].mc_data[j]; in ci_copy_vbios_smc_reg_table()
2575 ni_table->num_entries = table->num_entries; in ci_copy_vbios_smc_reg_table()
2581 struct ci_mc_reg_table *table) in ci_set_mc_special_registers() argument
2587 for (i = 0, j = table->last; i < table->last; i++) { in ci_set_mc_special_registers()
2589 "Invalid VramInfo table.", return -EINVAL); in ci_set_mc_special_registers()
2591 switch (table->mc_reg_address[i].s1) { in ci_set_mc_special_registers()
2595 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; in ci_set_mc_special_registers()
2596 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; in ci_set_mc_special_registers()
2597 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
2598 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
2600 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in ci_set_mc_special_registers()
2605 "Invalid VramInfo table.", return -EINVAL); in ci_set_mc_special_registers()
2607 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; in ci_set_mc_special_registers()
2608 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; in ci_set_mc_special_registers()
2609 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
2610 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
2612 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
2615 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in ci_set_mc_special_registers()
2621 "Invalid VramInfo table.", return -EINVAL); in ci_set_mc_special_registers()
2622 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; in ci_set_mc_special_registers()
2623 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; in ci_set_mc_special_registers()
2624 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
2625 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
2626 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in ci_set_mc_special_registers()
2635 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; in ci_set_mc_special_registers()
2636 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; in ci_set_mc_special_registers()
2637 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
2638 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
2640 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
2651 table->last = j; in ci_set_mc_special_registers()
2656 static int ci_set_valid_flag(struct ci_mc_reg_table *table) in ci_set_valid_flag() argument
2660 for (i = 0; i < table->last; i++) { in ci_set_valid_flag()
2661 for (j = 1; j < table->num_entries; j++) { in ci_set_valid_flag()
2662 if (table->mc_reg_table_entry[j-1].mc_data[i] != in ci_set_valid_flag()
2663 table->mc_reg_table_entry[j].mc_data[i]) { in ci_set_valid_flag()
2664 table->validflag |= (1 << i); in ci_set_valid_flag()
2677 pp_atomctrl_mc_reg_table *table; in ci_initialize_mc_reg_table() local
2681 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL); in ci_initialize_mc_reg_table()
2683 if (NULL == table) in ci_initialize_mc_reg_table()
2708 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); in ci_initialize_mc_reg_table()
2711 result = ci_copy_vbios_smc_reg_table(table, ni_table); in ci_initialize_mc_reg_table()
2721 kfree(table); in ci_initialize_mc_reg_table()