Lines Matching refs:dyn_state
1213 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1214 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1215 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1216 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in init_clock_voltage_dependency()
1217 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1218 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1219 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1220 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1221 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1222 hwmgr->dyn_state.ppm_parameter_table = NULL; in init_clock_voltage_dependency()
1223 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1237 &hwmgr->dyn_state.vce_clock_voltage_dependency_table, in init_clock_voltage_dependency()
1252 &hwmgr->dyn_state.uvd_clock_voltage_dependency_table, ptable, array); in init_clock_voltage_dependency()
1263 &hwmgr->dyn_state.samu_clock_voltage_dependency_table, ptable); in init_clock_voltage_dependency()
1274 &hwmgr->dyn_state.acp_clock_voltage_dependency_table, ptable); in init_clock_voltage_dependency()
1285 result = get_cac_tdp_table(hwmgr, &hwmgr->dyn_state.cac_dtp_table, in init_clock_voltage_dependency()
1288 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = in init_clock_voltage_dependency()
1295 &hwmgr->dyn_state.cac_dtp_table, in init_clock_voltage_dependency()
1309 &hwmgr->dyn_state.vddc_dependency_on_sclk, table); in init_clock_voltage_dependency()
1317 &hwmgr->dyn_state.vddci_dependency_on_mclk, table); in init_clock_voltage_dependency()
1325 &hwmgr->dyn_state.vddc_dependency_on_mclk, table); in init_clock_voltage_dependency()
1333 &hwmgr->dyn_state.max_clock_voltage_on_dc, limit_table); in init_clock_voltage_dependency()
1336 if (result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) && in init_clock_voltage_dependency()
1337 (0 != hwmgr->dyn_state.vddc_dependency_on_mclk->count)) in init_clock_voltage_dependency()
1338 result = get_valid_clk(hwmgr, &hwmgr->dyn_state.valid_mclk_values, in init_clock_voltage_dependency()
1339 hwmgr->dyn_state.vddc_dependency_on_mclk); in init_clock_voltage_dependency()
1341 if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) && in init_clock_voltage_dependency()
1342 (0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count)) in init_clock_voltage_dependency()
1344 &hwmgr->dyn_state.valid_sclk_values, in init_clock_voltage_dependency()
1345 hwmgr->dyn_state.vddc_dependency_on_sclk); in init_clock_voltage_dependency()
1352 &hwmgr->dyn_state.mvdd_dependency_on_mclk, table); in init_clock_voltage_dependency()
1363 &hwmgr->dyn_state.vdd_gfx_dependency_on_sclk, table); in init_clock_voltage_dependency()
1424 hwmgr->dyn_state.ppm_parameter_table = ptr; in get_platform_power_management_table()
1470 hwmgr->dyn_state.cac_leakage_table = NULL; in init_dpm2_parameters()
1477 &hwmgr->dyn_state.cac_leakage_table, pCAC_leakage_table); in init_dpm2_parameters()
1482 hwmgr->dyn_state.ppm_parameter_table = NULL; in init_dpm2_parameters()
1538 hwmgr->dyn_state.vddc_phase_shed_limits_table = table; in init_phase_shedding_table()
1650 kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); in pp_tables_uninitialize()
1651 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in pp_tables_uninitialize()
1653 kfree(hwmgr->dyn_state.vddci_dependency_on_mclk); in pp_tables_uninitialize()
1654 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; in pp_tables_uninitialize()
1656 kfree(hwmgr->dyn_state.vddc_dependency_on_mclk); in pp_tables_uninitialize()
1657 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; in pp_tables_uninitialize()
1659 kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk); in pp_tables_uninitialize()
1660 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; in pp_tables_uninitialize()
1662 kfree(hwmgr->dyn_state.valid_mclk_values); in pp_tables_uninitialize()
1663 hwmgr->dyn_state.valid_mclk_values = NULL; in pp_tables_uninitialize()
1665 kfree(hwmgr->dyn_state.valid_sclk_values); in pp_tables_uninitialize()
1666 hwmgr->dyn_state.valid_sclk_values = NULL; in pp_tables_uninitialize()
1668 kfree(hwmgr->dyn_state.cac_leakage_table); in pp_tables_uninitialize()
1669 hwmgr->dyn_state.cac_leakage_table = NULL; in pp_tables_uninitialize()
1671 kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table); in pp_tables_uninitialize()
1672 hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL; in pp_tables_uninitialize()
1674 kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table); in pp_tables_uninitialize()
1675 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1677 kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table); in pp_tables_uninitialize()
1678 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1680 kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table); in pp_tables_uninitialize()
1681 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1683 kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table); in pp_tables_uninitialize()
1684 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; in pp_tables_uninitialize()
1686 kfree(hwmgr->dyn_state.cac_dtp_table); in pp_tables_uninitialize()
1687 hwmgr->dyn_state.cac_dtp_table = NULL; in pp_tables_uninitialize()
1689 kfree(hwmgr->dyn_state.ppm_parameter_table); in pp_tables_uninitialize()
1690 hwmgr->dyn_state.ppm_parameter_table = NULL; in pp_tables_uninitialize()
1692 kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk); in pp_tables_uninitialize()
1693 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL; in pp_tables_uninitialize()