Lines Matching full:enum
50 typedef enum GDS_PERFCOUNT_SELECT {
180 * MEM_PWR_FORCE_CTRL enum
183 typedef enum MEM_PWR_FORCE_CTRL {
191 * MEM_PWR_FORCE_CTRL2 enum
194 typedef enum MEM_PWR_FORCE_CTRL2 {
200 * MEM_PWR_DIS_CTRL enum
203 typedef enum MEM_PWR_DIS_CTRL {
209 * MEM_PWR_SEL_CTRL enum
212 typedef enum MEM_PWR_SEL_CTRL {
219 * MEM_PWR_SEL_CTRL2 enum
222 typedef enum MEM_PWR_SEL_CTRL2 {
228 * RowSize enum
231 typedef enum RowSize {
238 * SurfaceEndian enum
241 typedef enum SurfaceEndian {
249 * ArrayMode enum
252 typedef enum ArrayMode {
272 * NumPipes enum
275 typedef enum NumPipes {
285 * NumBanksConfig enum
288 typedef enum NumBanksConfig {
297 * PipeInterleaveSize enum
300 typedef enum PipeInterleaveSize {
308 * BankInterleaveSize enum
311 typedef enum BankInterleaveSize {
319 * NumShaderEngines enum
322 typedef enum NumShaderEngines {
330 * NumRbPerShaderEngine enum
333 typedef enum NumRbPerShaderEngine {
340 * NumGPUs enum
343 typedef enum NumGPUs {
351 * NumMaxCompressedFragments enum
354 typedef enum NumMaxCompressedFragments {
362 * ShaderEngineTileSize enum
365 typedef enum ShaderEngineTileSize {
371 * MultiGPUTileSize enum
374 typedef enum MultiGPUTileSize {
382 * NumLowerPipes enum
385 typedef enum NumLowerPipes {
391 * ColorTransform enum
394 typedef enum ColorTransform {
402 * CompareRef enum
405 typedef enum CompareRef {
417 * ReadSize enum
420 typedef enum ReadSize {
426 * DepthFormat enum
429 typedef enum DepthFormat {
441 * ZFormat enum
444 typedef enum ZFormat {
452 * StencilFormat enum
455 typedef enum StencilFormat {
461 * CmaskMode enum
464 typedef enum CmaskMode {
484 * QuadExportFormat enum
487 typedef enum QuadExportFormat {
503 * QuadExportFormatOld enum
506 typedef enum QuadExportFormatOld {
516 * ColorFormat enum
519 typedef enum ColorFormat {
555 * SurfaceFormat enum
558 typedef enum SurfaceFormat {
626 * BUF_DATA_FORMAT enum
629 typedef enum BUF_DATA_FORMAT {
649 * IMG_DATA_FORMAT enum
652 typedef enum IMG_DATA_FORMAT {
720 * BUF_NUM_FORMAT enum
723 typedef enum BUF_NUM_FORMAT {
735 * IMG_NUM_FORMAT enum
738 typedef enum IMG_NUM_FORMAT {
758 * IMG_NUM_FORMAT_FMASK enum
761 typedef enum IMG_NUM_FORMAT_FMASK {
781 * IMG_NUM_FORMAT_N_IN_16 enum
784 typedef enum IMG_NUM_FORMAT_N_IN_16 {
804 * IMG_NUM_FORMAT_ASTC_2D enum
807 typedef enum IMG_NUM_FORMAT_ASTC_2D {
827 * IMG_NUM_FORMAT_ASTC_3D enum
830 typedef enum IMG_NUM_FORMAT_ASTC_3D {
850 * TileType enum
853 typedef enum TileType {
859 * NonDispTilingOrder enum
862 typedef enum NonDispTilingOrder {
868 * MicroTileMode enum
871 typedef enum MicroTileMode {
880 * TileSplit enum
883 typedef enum TileSplit {
894 * SampleSplit enum
897 typedef enum SampleSplit {
905 * PipeConfig enum
908 typedef enum PipeConfig {
930 * SeEnable enum
933 typedef enum SeEnable {
939 * NumBanks enum
942 typedef enum NumBanks {
950 * BankWidth enum
953 typedef enum BankWidth {
961 * BankHeight enum
964 typedef enum BankHeight {
972 * BankWidthHeight enum
975 typedef enum BankWidthHeight {
983 * MacroTileAspect enum
986 typedef enum MacroTileAspect {
994 * GATCL1RequestType enum
997 typedef enum GATCL1RequestType {
1004 * UTCL1RequestType enum
1007 typedef enum UTCL1RequestType {
1014 * UTCL1FaultType enum
1017 typedef enum UTCL1FaultType {
1025 * TCC_CACHE_POLICIES enum
1028 typedef enum TCC_CACHE_POLICIES {
1034 * MTYPE enum
1037 typedef enum MTYPE {
1045 * RMI_CID enum
1048 typedef enum RMI_CID {
1060 * PERFMON_COUNTER_MODE enum
1063 typedef enum PERFMON_COUNTER_MODE {
1078 * PERFMON_SPM_MODE enum
1081 typedef enum PERFMON_SPM_MODE {
1096 * SurfaceTiling enum
1099 typedef enum SurfaceTiling {
1105 * SurfaceArray enum
1108 typedef enum SurfaceArray {
1116 * ColorArray enum
1119 typedef enum ColorArray {
1126 * DepthArray enum
1129 typedef enum DepthArray {
1135 * ENUM_NUM_SIMD_PER_CU enum
1138 typedef enum ENUM_NUM_SIMD_PER_CU {
1143 * DSM_ENABLE_ERROR_INJECT enum
1146 typedef enum DSM_ENABLE_ERROR_INJECT {
1154 * DSM_SELECT_INJECT_DELAY enum
1157 typedef enum DSM_SELECT_INJECT_DELAY {
1163 * SWIZZLE_TYPE_ENUM enum
1166 typedef enum SWIZZLE_TYPE_ENUM {
1175 * TC_MICRO_TILE_MODE enum
1178 typedef enum TC_MICRO_TILE_MODE {
1190 * SWIZZLE_MODE_ENUM enum
1193 typedef enum SWIZZLE_MODE_ENUM {
1233 * PipeTiling enum
1236 typedef enum PipeTiling {
1244 * BankTiling enum
1247 typedef enum BankTiling {
1253 * GroupInterleave enum
1256 typedef enum GroupInterleave {
1262 * RowTiling enum
1265 typedef enum RowTiling {
1277 * BankSwapBytes enum
1280 typedef enum BankSwapBytes {
1288 * SampleSplitBytes enum
1291 typedef enum SampleSplitBytes {
1303 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
1306 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
1312 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
1315 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
1321 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
1324 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
1330 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
1333 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
1339 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
1342 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
1348 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
1351 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
1357 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
1360 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
1366 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
1369 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
1375 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
1378 typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
1384 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
1387 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
1393 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
1396 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
1405 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
1408 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
1420 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
1423 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
1433 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
1436 typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
1460 * BLNDV_CONTROL_BLND_MODE enum
1463 typedef enum BLNDV_CONTROL_BLND_MODE {
1471 * BLNDV_CONTROL_BLND_STEREO_TYPE enum
1474 typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
1482 * BLNDV_CONTROL_BLND_STEREO_POLARITY enum
1485 typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
1491 * BLNDV_CONTROL_BLND_FEEDTHROUGH_EN enum
1494 typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
1500 * BLNDV_CONTROL_BLND_ALPHA_MODE enum
1503 typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
1511 * BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
1514 typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
1520 * BLNDV_CONTROL_BLND_MULTIPLIED_MODE enum
1523 typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
1529 * BLNDV_SM_CONTROL2_SM_MODE enum
1532 typedef enum BLNDV_SM_CONTROL2_SM_MODE {
1540 * BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE enum
1543 typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
1549 * BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE enum
1552 typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
1558 * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
1561 typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
1569 * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
1572 typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
1580 * BLNDV_CONTROL2_PTI_ENABLE enum
1583 typedef enum BLNDV_CONTROL2_PTI_ENABLE {
1589 * BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
1592 typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
1598 * BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
1601 typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
1607 * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
1610 typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
1616 * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
1619 typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
1625 * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
1628 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
1634 * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
1637 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
1643 * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
1646 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
1652 * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
1655 typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
1661 * BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
1664 typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
1670 * BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
1673 typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
1679 * BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
1682 typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
1688 * BLNDV_DEBUG_BLND_CNV_MUX_SELECT enum
1691 typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
1697 * BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
1700 typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
1710 * LBV_PIXEL_DEPTH enum
1713 typedef enum LBV_PIXEL_DEPTH {
1721 * LBV_PIXEL_EXPAN_MODE enum
1724 typedef enum LBV_PIXEL_EXPAN_MODE {
1730 * LBV_INTERLEAVE_EN enum
1733 typedef enum LBV_INTERLEAVE_EN {
1739 * LBV_PIXEL_REDUCE_MODE enum
1742 typedef enum LBV_PIXEL_REDUCE_MODE {
1748 * LBV_DYNAMIC_PIXEL_DEPTH enum
1751 typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
1757 * LBV_DITHER_EN enum
1760 typedef enum LBV_DITHER_EN {
1766 * LBV_DOWNSCALE_PREFETCH_EN enum
1769 typedef enum LBV_DOWNSCALE_PREFETCH_EN {
1775 * LBV_MEMORY_CONFIG enum
1778 typedef enum LBV_MEMORY_CONFIG {
1786 * LBV_SYNC_RESET_SEL2 enum
1789 typedef enum LBV_SYNC_RESET_SEL2 {
1795 * LBV_SYNC_DURATION enum
1798 typedef enum LBV_SYNC_DURATION {
1810 * CRTC_CONTROL_CRTC_START_POINT_CNTL enum
1813 typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
1819 * CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL enum
1822 typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
1828 * CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL enum
1831 typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
1839 * CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY enum
1842 typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
1848 * CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE enum
1851 typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
1857 * CRTC_CONTROL_CRTC_SOF_PULL_EN enum
1860 typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
1866 * CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL enum
1869 typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
1875 * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL enum
1878 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
1884 * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL enum
1887 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
1893 * CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN enum
1896 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
1902 * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC enum
1905 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
1911 * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT enum
1914 typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
1920 * CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
1923 typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
1929 * CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR enum
1932 typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
1938 * CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL enum
1941 typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
1947 * CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN enum
1950 typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
1956 * CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT enum
1959 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
1983 * CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT enum
1986 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
1997 * CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN enum
2000 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
2006 * CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR enum
2009 typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
2015 * CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT enum
2018 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
2042 * CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT enum
2045 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
2056 * CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN enum
2059 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
2065 * CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR enum
2068 typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
2074 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE enum
2077 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
2085 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK enum
2088 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
2094 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL enum
2097 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
2103 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR enum
2106 typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
2112 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT enum
2115 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
2135 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY enum
2138 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
2144 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY enum
2147 typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
2153 * CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE enum
2156 typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
2164 * CRTC_CONTROL_CRTC_MASTER_EN enum
2167 typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
2173 * CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN enum
2176 typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
2182 * CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE enum
2185 typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
2191 * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE enum
2194 typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
2200 * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD enum
2203 typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
2211 * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY enum
2214 typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
2220 * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT enum
2223 typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
2229 * CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN enum
2232 typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
2238 * CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE enum
2241 typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
2247 * CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR enum
2250 typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
2256 * CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE enum
2259 typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
2267 * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY enum
2270 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
2276 * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY enum
2279 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
2285 * CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY enum
2288 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
2294 * CRTC_STEREO_CONTROL_CRTC_STEREO_EN enum
2297 typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
2303 * CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR enum
2306 typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
2312 * CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL enum
2315 typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
2323 * CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY enum
2326 typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
2332 * CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY enum
2335 typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
2341 * CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN enum
2344 typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
2350 * CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN enum
2353 typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
2359 * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK enum
2362 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
2368 * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE enum
2371 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
2377 * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK enum
2380 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
2386 * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE enum
2389 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
2395 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK enum
2398 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
2404 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE enum
2407 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
2413 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
2416 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
2422 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
2425 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
2431 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK enum
2434 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
2440 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE enum
2443 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
2449 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK enum
2452 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
2458 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE enum
2461 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
2467 * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK enum
2470 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
2476 * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE enum
2479 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
2485 * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK enum
2488 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
2494 * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE enum
2497 typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
2503 * CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK enum
2506 typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
2512 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY enum
2515 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
2521 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN enum
2524 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
2530 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE enum
2533 typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE {
2539 * CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE enum
2542 typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
2548 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN enum
2551 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
2557 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE enum
2560 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
2572 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE enum
2575 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
2581 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT enum
2584 typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
2592 * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
2595 typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
2601 * MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK enum
2604 typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
2610 * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum
2613 typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
2619 * MASTER_UPDATE_MODE_MASTER_UPDATE_MODE enum
2622 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
2630 * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
2633 typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
2641 * CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE enum
2644 typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
2651 * CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR enum
2654 typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
2660 * CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR enum
2663 typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
2669 * CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR enum
2672 typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
2678 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
2681 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
2687 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE enum
2690 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
2696 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR enum
2699 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
2705 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE enum
2708 typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
2714 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR enum
2717 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
2723 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE enum
2726 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
2732 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE enum
2735 typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
2741 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR enum
2744 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
2750 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE enum
2753 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
2759 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE enum
2762 typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
2768 * CRTC_CRC_CNTL_CRTC_CRC_EN enum
2771 typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
2777 * CRTC_CRC_CNTL_CRTC_CRC_CONT_EN enum
2780 typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
2786 * CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE enum
2789 typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
2797 * CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE enum
2800 typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
2808 * CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS enum
2811 typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
2817 * CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT enum
2820 typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
2832 * CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT enum
2835 typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
2847 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE enum
2850 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
2858 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum
2861 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
2867 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum
2870 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
2876 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum
2879 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
2887 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE enum
2890 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
2896 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE enum
2899 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
2905 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY enum
2908 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
2914 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY enum
2917 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
2923 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE enum
2926 typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
2932 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum
2935 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
2941 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR enum
2944 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
2950 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE enum
2953 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
2959 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum
2962 typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
2974 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE enum
2977 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
2983 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR enum
2986 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
2992 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE enum
2995 typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
3001 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum
3004 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
3010 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR enum
3013 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
3019 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum
3022 typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
3028 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE enum
3031 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
3037 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR enum
3040 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
3046 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE enum
3049 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
3055 * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE enum
3058 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
3064 * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE enum
3067 typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
3073 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN enum
3076 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
3082 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB enum
3085 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
3091 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE enum
3094 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
3102 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR enum
3105 typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
3111 * CRTC_V_SYNC_A_POL enum
3114 typedef enum CRTC_V_SYNC_A_POL {
3120 * CRTC_H_SYNC_A_POL enum
3123 typedef enum CRTC_H_SYNC_A_POL {
3129 * CRTC_HORZ_REPETITION_COUNT enum
3132 typedef enum CRTC_HORZ_REPETITION_COUNT {
3152 * CRTC_DRR_MODE_DBUF_UPDATE_MODE enum
3155 typedef enum CRTC_DRR_MODE_DBUF_UPDATE_MODE {
3167 * FMT_CONTROL_PIXEL_ENCODING enum
3170 typedef enum FMT_CONTROL_PIXEL_ENCODING {
3178 * FMT_CONTROL_SUBSAMPLING_MODE enum
3181 typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3189 * FMT_CONTROL_SUBSAMPLING_ORDER enum
3192 typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3198 * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3201 typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3207 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3210 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3216 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3219 typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3226 * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3229 typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3236 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3239 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3246 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3249 typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3255 * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3258 typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3266 * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3269 typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3277 * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3280 typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3288 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT enum
3291 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
3297 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3300 typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3306 * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3309 typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3321 * FMT_CRC_CNTL_CONT_EN enum
3324 typedef enum FMT_CRC_CNTL_CONT_EN {
3330 * FMT_CRC_CNTL_INCLUDE_OVERSCAN enum
3333 typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
3339 * FMT_CRC_CNTL_ONLY_BLANKB enum
3342 typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
3348 * FMT_CRC_CNTL_PSR_MODE_ENABLE enum
3351 typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
3357 * FMT_CRC_CNTL_INTERLACE_MODE enum
3360 typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
3368 * FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE enum
3371 typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
3377 * FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT enum
3380 typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
3386 * FMT_DEBUG_CNTL_COLOR_SELECT enum
3389 typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3397 * FMT_SPATIAL_DITHER_MODE enum
3400 typedef enum FMT_SPATIAL_DITHER_MODE {
3408 * FMT_STEREOSYNC_OVR_POL enum
3411 typedef enum FMT_STEREOSYNC_OVR_POL {
3417 * FMT_DYNAMIC_EXP_MODE enum
3420 typedef enum FMT_DYNAMIC_EXP_MODE {
3430 * HPD_INT_CONTROL_ACK enum
3433 typedef enum HPD_INT_CONTROL_ACK {
3439 * HPD_INT_CONTROL_POLARITY enum
3442 typedef enum HPD_INT_CONTROL_POLARITY {
3448 * HPD_INT_CONTROL_RX_INT_ACK enum
3451 typedef enum HPD_INT_CONTROL_RX_INT_ACK {
3461 * LB_DATA_FORMAT_PIXEL_DEPTH enum
3464 typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
3472 * LB_DATA_FORMAT_PIXEL_EXPAN_MODE enum
3475 typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
3481 * LB_DATA_FORMAT_PIXEL_REDUCE_MODE enum
3484 typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
3490 * LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH enum
3493 typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
3499 * LB_DATA_FORMAT_INTERLEAVE_EN enum
3502 typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
3508 * LB_DATA_FORMAT_REQUEST_MODE enum
3511 typedef enum LB_DATA_FORMAT_REQUEST_MODE {
3517 * LB_DATA_FORMAT_ALPHA_EN enum
3520 typedef enum LB_DATA_FORMAT_ALPHA_EN {
3526 * LB_VLINE_START_END_VLINE_INV enum
3529 typedef enum LB_VLINE_START_END_VLINE_INV {
3535 * LB_VLINE2_START_END_VLINE2_INV enum
3538 typedef enum LB_VLINE2_START_END_VLINE2_INV {
3544 * LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK enum
3547 typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
3553 * LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK enum
3556 typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
3562 * LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK enum
3565 typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
3571 * LB_VLINE_STATUS_VLINE_ACK enum
3574 typedef enum LB_VLINE_STATUS_VLINE_ACK {
3580 * LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE enum
3583 typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
3589 * LB_VLINE2_STATUS_VLINE2_ACK enum
3592 typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
3598 * LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE enum
3601 typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
3607 * LB_VBLANK_STATUS_VBLANK_ACK enum
3610 typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
3616 * LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE enum
3619 typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
3625 * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL enum
3628 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
3636 * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 enum
3639 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
3645 * LB_SYNC_RESET_SEL_LB_SYNC_DURATION enum
3648 typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
3656 * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN enum
3659 typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
3665 * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN enum
3668 typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
3674 * LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK enum
3677 typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
3683 * LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK enum
3686 typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
3692 * LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE enum
3695 typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
3701 * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET enum
3704 typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
3710 * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK enum
3713 typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
3719 * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE enum
3722 typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
3729 * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE enum
3732 typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
3738 * LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE enum
3741 typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
3747 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL enum
3750 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
3756 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE enum
3759 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
3765 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO enum
3768 typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
3774 * LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN enum
3777 typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
3787 * HDMI_KEEPOUT_MODE enum
3790 typedef enum HDMI_KEEPOUT_MODE {
3796 * HDMI_DATA_SCRAMBLE_EN enum
3799 typedef enum HDMI_DATA_SCRAMBLE_EN {
3805 * HDMI_CLOCK_CHANNEL_RATE enum
3808 typedef enum HDMI_CLOCK_CHANNEL_RATE {
3814 * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
3817 typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
3823 * HDMI_PACKET_GEN_VERSION enum
3826 typedef enum HDMI_PACKET_GEN_VERSION {
3832 * HDMI_ERROR_ACK enum
3835 typedef enum HDMI_ERROR_ACK {
3841 * HDMI_ERROR_MASK enum
3844 typedef enum HDMI_ERROR_MASK {
3850 * HDMI_DEEP_COLOR_DEPTH enum
3853 typedef enum HDMI_DEEP_COLOR_DEPTH {
3861 * HDMI_AUDIO_DELAY_EN enum
3864 typedef enum HDMI_AUDIO_DELAY_EN {
3872 * HDMI_AUDIO_SEND_MAX_PACKETS enum
3875 typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
3881 * HDMI_ACR_SEND enum
3884 typedef enum HDMI_ACR_SEND {
3890 * HDMI_ACR_CONT enum
3893 typedef enum HDMI_ACR_CONT {
3899 * HDMI_ACR_SELECT enum
3902 typedef enum HDMI_ACR_SELECT {
3910 * HDMI_ACR_SOURCE enum
3913 typedef enum HDMI_ACR_SOURCE {
3919 * HDMI_ACR_N_MULTIPLE enum
3922 typedef enum HDMI_ACR_N_MULTIPLE {
3934 * HDMI_ACR_AUDIO_PRIORITY enum
3937 typedef enum HDMI_ACR_AUDIO_PRIORITY {
3943 * HDMI_NULL_SEND enum
3946 typedef enum HDMI_NULL_SEND {
3952 * HDMI_GC_SEND enum
3955 typedef enum HDMI_GC_SEND {
3961 * HDMI_GC_CONT enum
3964 typedef enum HDMI_GC_CONT {
3970 * HDMI_ISRC_SEND enum
3973 typedef enum HDMI_ISRC_SEND {
3979 * HDMI_ISRC_CONT enum
3982 typedef enum HDMI_ISRC_CONT {
3988 * HDMI_AVI_INFO_SEND enum
3991 typedef enum HDMI_AVI_INFO_SEND {
3997 * HDMI_AVI_INFO_CONT enum
4000 typedef enum HDMI_AVI_INFO_CONT {
4006 * HDMI_AUDIO_INFO_SEND enum
4009 typedef enum HDMI_AUDIO_INFO_SEND {
4015 * HDMI_AUDIO_INFO_CONT enum
4018 typedef enum HDMI_AUDIO_INFO_CONT {
4024 * HDMI_MPEG_INFO_SEND enum
4027 typedef enum HDMI_MPEG_INFO_SEND {
4033 * HDMI_MPEG_INFO_CONT enum
4036 typedef enum HDMI_MPEG_INFO_CONT {
4042 * HDMI_GENERIC0_SEND enum
4045 typedef enum HDMI_GENERIC0_SEND {
4051 * HDMI_GENERIC0_CONT enum
4054 typedef enum HDMI_GENERIC0_CONT {
4060 * HDMI_GENERIC1_SEND enum
4063 typedef enum HDMI_GENERIC1_SEND {
4069 * HDMI_GENERIC1_CONT enum
4072 typedef enum HDMI_GENERIC1_CONT {
4078 * HDMI_GC_AVMUTE_CONT enum
4081 typedef enum HDMI_GC_AVMUTE_CONT {
4087 * HDMI_PACKING_PHASE_OVERRIDE enum
4090 typedef enum HDMI_PACKING_PHASE_OVERRIDE {
4096 * HDMI_GENERIC2_SEND enum
4099 typedef enum HDMI_GENERIC2_SEND {
4105 * HDMI_GENERIC2_CONT enum
4108 typedef enum HDMI_GENERIC2_CONT {
4114 * HDMI_GENERIC3_SEND enum
4117 typedef enum HDMI_GENERIC3_SEND {
4123 * HDMI_GENERIC3_CONT enum
4126 typedef enum HDMI_GENERIC3_CONT {
4132 * TMDS_PIXEL_ENCODING enum
4135 typedef enum TMDS_PIXEL_ENCODING {
4141 * TMDS_COLOR_FORMAT enum
4144 typedef enum TMDS_COLOR_FORMAT {
4152 * TMDS_STEREOSYNC_CTL_SEL_REG enum
4155 typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
4163 * TMDS_CTL0_DATA_SEL enum
4166 typedef enum TMDS_CTL0_DATA_SEL {
4178 * TMDS_CTL0_DATA_INVERT enum
4181 typedef enum TMDS_CTL0_DATA_INVERT {
4187 * TMDS_CTL0_DATA_MODULATION enum
4190 typedef enum TMDS_CTL0_DATA_MODULATION {
4198 * TMDS_CTL0_PATTERN_OUT_EN enum
4201 typedef enum TMDS_CTL0_PATTERN_OUT_EN {
4207 * TMDS_CTL1_DATA_SEL enum
4210 typedef enum TMDS_CTL1_DATA_SEL {
4222 * TMDS_CTL1_DATA_INVERT enum
4225 typedef enum TMDS_CTL1_DATA_INVERT {
4231 * TMDS_CTL1_DATA_MODULATION enum
4234 typedef enum TMDS_CTL1_DATA_MODULATION {
4242 * TMDS_CTL1_PATTERN_OUT_EN enum
4245 typedef enum TMDS_CTL1_PATTERN_OUT_EN {
4251 * TMDS_CTL2_DATA_SEL enum
4254 typedef enum TMDS_CTL2_DATA_SEL {
4266 * TMDS_CTL2_DATA_INVERT enum
4269 typedef enum TMDS_CTL2_DATA_INVERT {
4275 * TMDS_CTL2_DATA_MODULATION enum
4278 typedef enum TMDS_CTL2_DATA_MODULATION {
4286 * TMDS_CTL2_PATTERN_OUT_EN enum
4289 typedef enum TMDS_CTL2_PATTERN_OUT_EN {
4295 * TMDS_CTL3_DATA_INVERT enum
4298 typedef enum TMDS_CTL3_DATA_INVERT {
4304 * TMDS_CTL3_DATA_MODULATION enum
4307 typedef enum TMDS_CTL3_DATA_MODULATION {
4315 * TMDS_CTL3_PATTERN_OUT_EN enum
4318 typedef enum TMDS_CTL3_PATTERN_OUT_EN {
4324 * TMDS_CTL3_DATA_SEL enum
4327 typedef enum TMDS_CTL3_DATA_SEL {
4339 * DIG_FE_CNTL_SOURCE_SELECT enum
4342 typedef enum DIG_FE_CNTL_SOURCE_SELECT {
4352 * DIG_FE_CNTL_STEREOSYNC_SELECT enum
4355 typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
4365 * DIG_FIFO_READ_CLOCK_SRC enum
4368 typedef enum DIG_FIFO_READ_CLOCK_SRC {
4374 * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
4377 typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
4383 * DIG_OUTPUT_CRC_DATA_SEL enum
4386 typedef enum DIG_OUTPUT_CRC_DATA_SEL {
4394 * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
4397 typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
4403 * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
4406 typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
4412 * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
4415 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
4421 * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
4424 typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
4430 * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
4433 typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
4439 * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
4442 typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
4448 * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum
4451 typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
4457 * DIG_FIFO_ERROR_ACK enum
4460 typedef enum DIG_FIFO_ERROR_ACK {
4466 * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum
4469 typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
4475 * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum
4478 typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
4484 * AFMT_INTERRUPT_STATUS_CHG_MASK enum
4487 typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
4493 * HDMI_GC_AVMUTE enum
4496 typedef enum HDMI_GC_AVMUTE {
4502 * HDMI_DEFAULT_PAHSE enum
4505 typedef enum HDMI_DEFAULT_PAHSE {
4511 * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
4514 typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
4520 * AUDIO_LAYOUT_SELECT enum
4523 typedef enum AUDIO_LAYOUT_SELECT {
4529 * AFMT_AUDIO_CRC_CONTROL_CONT enum
4532 typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
4538 * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
4541 typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
4547 * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
4550 typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
4570 * AFMT_RAMP_CONTROL0_SIGN enum
4573 typedef enum AFMT_RAMP_CONTROL0_SIGN {
4579 * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
4582 typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
4588 * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
4591 typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
4597 * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
4600 typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
4606 * AFMT_AUDIO_SRC_CONTROL_SELECT enum
4609 typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
4620 * DIG_BE_CNTL_MODE enum
4623 typedef enum DIG_BE_CNTL_MODE {
4635 * DIG_BE_CNTL_HPD_SELECT enum
4638 typedef enum DIG_BE_CNTL_HPD_SELECT {
4648 * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
4651 typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
4657 * TMDS_SYNC_PHASE enum
4660 typedef enum TMDS_SYNC_PHASE {
4666 * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
4669 typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
4675 * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
4678 typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
4684 * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
4687 typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
4693 * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
4696 typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
4702 * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
4705 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
4713 * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
4716 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
4722 * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
4725 typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
4731 * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
4734 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
4740 * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
4743 typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
4749 * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
4752 typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
4758 * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
4761 typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
4767 * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
4770 typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
4776 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
4779 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
4785 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
4788 typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
4794 * TMDS_REG_TEST_OUTPUTA_CNTLA enum
4797 typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
4805 * TMDS_REG_TEST_OUTPUTB_CNTLB enum
4808 typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
4820 * DCP_GRPH_ENABLE enum
4823 typedef enum DCP_GRPH_ENABLE {
4829 * DCP_GRPH_KEYER_ALPHA_SEL enum
4832 typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
4838 * DCP_GRPH_DEPTH enum
4841 typedef enum DCP_GRPH_DEPTH {
4849 * DCP_GRPH_NUM_BANKS enum
4852 typedef enum DCP_GRPH_NUM_BANKS {
4861 * DCP_GRPH_NUM_PIPES enum
4864 typedef enum DCP_GRPH_NUM_PIPES {
4872 * DCP_GRPH_FORMAT enum
4875 typedef enum DCP_GRPH_FORMAT {
4883 * DCP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
4886 typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
4892 * DCP_GRPH_SW_MODE enum
4895 typedef enum DCP_GRPH_SW_MODE {
4908 * DCP_GRPH_COLOR_EXPANSION_MODE enum
4911 typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
4917 * DCP_GRPH_LUT_10BIT_BYPASS_EN enum
4920 typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
4926 * DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN enum
4929 typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
4935 * DCP_GRPH_ENDIAN_SWAP enum
4938 typedef enum DCP_GRPH_ENDIAN_SWAP {
4946 * DCP_GRPH_RED_CROSSBAR enum
4949 typedef enum DCP_GRPH_RED_CROSSBAR {
4957 * DCP_GRPH_GREEN_CROSSBAR enum
4960 typedef enum DCP_GRPH_GREEN_CROSSBAR {
4968 * DCP_GRPH_BLUE_CROSSBAR enum
4971 typedef enum DCP_GRPH_BLUE_CROSSBAR {
4979 * DCP_GRPH_ALPHA_CROSSBAR enum
4982 typedef enum DCP_GRPH_ALPHA_CROSSBAR {
4990 * DCP_GRPH_PRIMARY_DFQ_ENABLE enum
4993 typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
4999 * DCP_GRPH_SECONDARY_DFQ_ENABLE enum
5002 typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
5008 * DCP_GRPH_INPUT_GAMMA_MODE enum
5011 typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
5017 * DCP_GRPH_MODE_UPDATE_PENDING enum
5020 typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
5026 * DCP_GRPH_MODE_UPDATE_TAKEN enum
5029 typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
5035 * DCP_GRPH_SURFACE_UPDATE_PENDING enum
5038 typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
5044 * DCP_GRPH_SURFACE_UPDATE_TAKEN enum
5047 typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
5053 * DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE enum
5056 typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
5062 * DCP_GRPH_UPDATE_LOCK enum
5065 typedef enum DCP_GRPH_UPDATE_LOCK {
5071 * DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
5074 typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
5080 * DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
5083 typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
5089 * DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
5092 typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
5098 * DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN enum
5101 typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
5107 * DCP_GRPH_XDMA_SUPER_AA_EN enum
5110 typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
5116 * DCP_GRPH_DFQ_RESET enum
5119 typedef enum DCP_GRPH_DFQ_RESET {
5125 * DCP_GRPH_DFQ_SIZE enum
5128 typedef enum DCP_GRPH_DFQ_SIZE {
5140 * DCP_GRPH_DFQ_MIN_FREE_ENTRIES enum
5143 typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
5155 * DCP_GRPH_DFQ_RESET_ACK enum
5158 typedef enum DCP_GRPH_DFQ_RESET_ACK {
5164 * DCP_GRPH_PFLIP_INT_CLEAR enum
5167 typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
5173 * DCP_GRPH_PFLIP_INT_MASK enum
5176 typedef enum DCP_GRPH_PFLIP_INT_MASK {
5182 * DCP_GRPH_PFLIP_INT_TYPE enum
5185 typedef enum DCP_GRPH_PFLIP_INT_TYPE {
5191 * DCP_GRPH_PRESCALE_SELECT enum
5194 typedef enum DCP_GRPH_PRESCALE_SELECT {
5200 * DCP_GRPH_PRESCALE_R_SIGN enum
5203 typedef enum DCP_GRPH_PRESCALE_R_SIGN {
5209 * DCP_GRPH_PRESCALE_G_SIGN enum
5212 typedef enum DCP_GRPH_PRESCALE_G_SIGN {
5218 * DCP_GRPH_PRESCALE_B_SIGN enum
5221 typedef enum DCP_GRPH_PRESCALE_B_SIGN {
5227 * DCP_GRPH_PRESCALE_BYPASS enum
5230 typedef enum DCP_GRPH_PRESCALE_BYPASS {
5236 * DCP_INPUT_CSC_GRPH_MODE enum
5239 typedef enum DCP_INPUT_CSC_GRPH_MODE {
5247 * DCP_OUTPUT_CSC_GRPH_MODE enum
5250 typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
5262 * DCP_DENORM_MODE enum
5265 typedef enum DCP_DENORM_MODE {
5277 * DCP_DENORM_14BIT_OUT enum
5280 typedef enum DCP_DENORM_14BIT_OUT {
5286 * DCP_OUT_ROUND_TRUNC_MODE enum
5289 typedef enum DCP_OUT_ROUND_TRUNC_MODE {
5309 * DCP_KEY_MODE enum
5312 typedef enum DCP_KEY_MODE {
5320 * DCP_GRPH_DEGAMMA_MODE enum
5323 typedef enum DCP_GRPH_DEGAMMA_MODE {
5331 * DCP_CURSOR_DEGAMMA_MODE enum
5334 typedef enum DCP_CURSOR_DEGAMMA_MODE {
5342 * DCP_GRPH_GAMUT_REMAP_MODE enum
5345 typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
5353 * DCP_SPATIAL_DITHER_EN enum
5356 typedef enum DCP_SPATIAL_DITHER_EN {
5362 * DCP_SPATIAL_DITHER_MODE enum
5365 typedef enum DCP_SPATIAL_DITHER_MODE {
5373 * DCP_SPATIAL_DITHER_DEPTH enum
5376 typedef enum DCP_SPATIAL_DITHER_DEPTH {
5384 * DCP_FRAME_RANDOM_ENABLE enum
5387 typedef enum DCP_FRAME_RANDOM_ENABLE {
5393 * DCP_RGB_RANDOM_ENABLE enum
5396 typedef enum DCP_RGB_RANDOM_ENABLE {
5402 * DCP_HIGHPASS_RANDOM_ENABLE enum
5405 typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
5411 * DCP_CURSOR_EN enum
5414 typedef enum DCP_CURSOR_EN {
5420 * DCP_CUR_INV_TRANS_CLAMP enum
5423 typedef enum DCP_CUR_INV_TRANS_CLAMP {
5429 * DCP_CURSOR_MODE enum
5432 typedef enum DCP_CURSOR_MODE {
5440 * DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM enum
5443 typedef enum DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM {
5449 * DCP_CURSOR_2X_MAGNIFY enum
5452 typedef enum DCP_CURSOR_2X_MAGNIFY {
5458 * DCP_CURSOR_FORCE_MC_ON enum
5461 typedef enum DCP_CURSOR_FORCE_MC_ON {
5467 * DCP_CURSOR_URGENT_CONTROL enum
5470 typedef enum DCP_CURSOR_URGENT_CONTROL {
5479 * DCP_CURSOR_UPDATE_PENDING enum
5482 typedef enum DCP_CURSOR_UPDATE_PENDING {
5488 * DCP_CURSOR_UPDATE_TAKEN enum
5491 typedef enum DCP_CURSOR_UPDATE_TAKEN {
5497 * DCP_CURSOR_UPDATE_LOCK enum
5500 typedef enum DCP_CURSOR_UPDATE_LOCK {
5506 * DCP_CURSOR_DISABLE_MULTIPLE_UPDATE enum
5509 typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
5515 * DCP_CURSOR_UPDATE_STEREO_MODE enum
5518 typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
5526 * DCP_CUR2_INV_TRANS_CLAMP enum
5529 typedef enum DCP_CUR2_INV_TRANS_CLAMP {
5535 * DCP_CUR_REQUEST_FILTER_DIS enum
5538 typedef enum DCP_CUR_REQUEST_FILTER_DIS {
5544 * DCP_CURSOR_STEREO_EN enum
5547 typedef enum DCP_CURSOR_STEREO_EN {
5553 * DCP_CURSOR_STEREO_OFFSET_YNX enum
5556 typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
5562 * DCP_DC_LUT_RW_MODE enum
5565 typedef enum DCP_DC_LUT_RW_MODE {
5571 * DCP_DC_LUT_VGA_ACCESS_ENABLE enum
5574 typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
5580 * DCP_DC_LUT_AUTOFILL enum
5583 typedef enum DCP_DC_LUT_AUTOFILL {
5589 * DCP_DC_LUT_AUTOFILL_DONE enum
5592 typedef enum DCP_DC_LUT_AUTOFILL_DONE {
5598 * DCP_DC_LUT_INC_B enum
5601 typedef enum DCP_DC_LUT_INC_B {
5615 * DCP_DC_LUT_DATA_B_SIGNED_EN enum
5618 typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
5624 * DCP_DC_LUT_DATA_B_FLOAT_POINT_EN enum
5627 typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
5633 * DCP_DC_LUT_DATA_B_FORMAT enum
5636 typedef enum DCP_DC_LUT_DATA_B_FORMAT {
5644 * DCP_DC_LUT_INC_G enum
5647 typedef enum DCP_DC_LUT_INC_G {
5661 * DCP_DC_LUT_DATA_G_SIGNED_EN enum
5664 typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
5670 * DCP_DC_LUT_DATA_G_FLOAT_POINT_EN enum
5673 typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
5679 * DCP_DC_LUT_DATA_G_FORMAT enum
5682 typedef enum DCP_DC_LUT_DATA_G_FORMAT {
5690 * DCP_DC_LUT_INC_R enum
5693 typedef enum DCP_DC_LUT_INC_R {
5707 * DCP_DC_LUT_DATA_R_SIGNED_EN enum
5710 typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
5716 * DCP_DC_LUT_DATA_R_FLOAT_POINT_EN enum
5719 typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
5725 * DCP_DC_LUT_DATA_R_FORMAT enum
5728 typedef enum DCP_DC_LUT_DATA_R_FORMAT {
5736 * DCP_CRC_ENABLE enum
5739 typedef enum DCP_CRC_ENABLE {
5745 * DCP_CRC_SOURCE_SEL enum
5748 typedef enum DCP_CRC_SOURCE_SEL {
5756 * DCP_CRC_LINE_SEL enum
5759 typedef enum DCP_CRC_LINE_SEL {
5767 * DCP_GRPH_FLIP_RATE enum
5770 typedef enum DCP_GRPH_FLIP_RATE {
5782 * DCP_GRPH_FLIP_RATE_ENABLE enum
5785 typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
5791 * DCP_GSL0_EN enum
5794 typedef enum DCP_GSL0_EN {
5800 * DCP_GSL1_EN enum
5803 typedef enum DCP_GSL1_EN {
5809 * DCP_GSL2_EN enum
5812 typedef enum DCP_GSL2_EN {
5818 * DCP_GSL_MASTER_EN enum
5821 typedef enum DCP_GSL_MASTER_EN {
5827 * DCP_GSL_XDMA_GROUP enum
5830 typedef enum DCP_GSL_XDMA_GROUP {
5838 * DCP_GSL_XDMA_GROUP_UNDERFLOW_EN enum
5841 typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
5847 * DCP_GSL_SYNC_SOURCE enum
5850 typedef enum DCP_GSL_SYNC_SOURCE {
5858 * DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC enum
5861 typedef enum DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC {
5867 * DCP_GSL_DELAY_SURFACE_UPDATE_PENDING enum
5870 typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
5876 * DCP_TEST_DEBUG_WRITE_EN enum
5879 typedef enum DCP_TEST_DEBUG_WRITE_EN {
5885 * DCP_GRPH_STEREOSYNC_FLIP_EN enum
5888 typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
5894 * DCP_GRPH_STEREOSYNC_FLIP_MODE enum
5897 typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
5905 * DCP_GRPH_STEREOSYNC_SELECT_DISABLE enum
5908 typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
5914 * DCP_GRPH_ROTATION_ANGLE enum
5917 typedef enum DCP_GRPH_ROTATION_ANGLE {
5925 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN enum
5928 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
5934 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE enum
5937 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
5943 * DCP_GRPH_REGAMMA_MODE enum
5946 typedef enum DCP_GRPH_REGAMMA_MODE {
5955 * DCP_ALPHA_ROUND_TRUNC_MODE enum
5958 typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
5964 * DCP_CURSOR_ALPHA_BLND_ENA enum
5967 typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
5973 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK enum
5976 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
5982 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK enum
5985 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
5991 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK enum
5994 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
6000 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK enum
6003 typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
6009 * DCP_GRPH_SURFACE_COUNTER_EN enum
6012 typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
6018 * DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT enum
6021 typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
6037 * DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED enum
6040 typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
6046 * DCP_GRPH_XDMA_FLIP_TYPE_CLEAR enum
6049 typedef enum DCP_GRPH_XDMA_FLIP_TYPE_CLEAR {
6055 * DCP_GRPH_XDMA_DRR_MODE_ENABLE enum
6058 typedef enum DCP_GRPH_XDMA_DRR_MODE_ENABLE {
6064 * DCP_GRPH_XDMA_MULTIFLIP_ENABLE enum
6067 typedef enum DCP_GRPH_XDMA_MULTIFLIP_ENABLE {
6073 * DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK enum
6076 typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK {
6082 * DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK enum
6085 typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK {
6095 * PERFCOUNTER_CVALUE_SEL enum
6098 typedef enum PERFCOUNTER_CVALUE_SEL {
6110 * PERFCOUNTER_INC_MODE enum
6113 typedef enum PERFCOUNTER_INC_MODE {
6122 * PERFCOUNTER_HW_CNTL_SEL enum
6125 typedef enum PERFCOUNTER_HW_CNTL_SEL {
6131 * PERFCOUNTER_RUNEN_MODE enum
6134 typedef enum PERFCOUNTER_RUNEN_MODE {
6140 * PERFCOUNTER_CNTOFF_START_DIS enum
6143 typedef enum PERFCOUNTER_CNTOFF_START_DIS {
6149 * PERFCOUNTER_RESTART_EN enum
6152 typedef enum PERFCOUNTER_RESTART_EN {
6158 * PERFCOUNTER_INT_EN enum
6161 typedef enum PERFCOUNTER_INT_EN {
6167 * PERFCOUNTER_OFF_MASK enum
6170 typedef enum PERFCOUNTER_OFF_MASK {
6176 * PERFCOUNTER_ACTIVE enum
6179 typedef enum PERFCOUNTER_ACTIVE {
6185 * PERFCOUNTER_INT_TYPE enum
6188 typedef enum PERFCOUNTER_INT_TYPE {
6194 * PERFCOUNTER_COUNTED_VALUE_TYPE enum
6197 typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
6204 * PERFCOUNTER_CNTL_SEL enum
6207 typedef enum PERFCOUNTER_CNTL_SEL {
6219 * PERFCOUNTER_CNT0_STATE enum
6222 typedef enum PERFCOUNTER_CNT0_STATE {
6230 * PERFCOUNTER_STATE_SEL0 enum
6233 typedef enum PERFCOUNTER_STATE_SEL0 {
6239 * PERFCOUNTER_CNT1_STATE enum
6242 typedef enum PERFCOUNTER_CNT1_STATE {
6250 * PERFCOUNTER_STATE_SEL1 enum
6253 typedef enum PERFCOUNTER_STATE_SEL1 {
6259 * PERFCOUNTER_CNT2_STATE enum
6262 typedef enum PERFCOUNTER_CNT2_STATE {
6270 * PERFCOUNTER_STATE_SEL2 enum
6273 typedef enum PERFCOUNTER_STATE_SEL2 {
6279 * PERFCOUNTER_CNT3_STATE enum
6282 typedef enum PERFCOUNTER_CNT3_STATE {
6290 * PERFCOUNTER_STATE_SEL3 enum
6293 typedef enum PERFCOUNTER_STATE_SEL3 {
6299 * PERFCOUNTER_CNT4_STATE enum
6302 typedef enum PERFCOUNTER_CNT4_STATE {
6310 * PERFCOUNTER_STATE_SEL4 enum
6313 typedef enum PERFCOUNTER_STATE_SEL4 {
6319 * PERFCOUNTER_CNT5_STATE enum
6322 typedef enum PERFCOUNTER_CNT5_STATE {
6330 * PERFCOUNTER_STATE_SEL5 enum
6333 typedef enum PERFCOUNTER_STATE_SEL5 {
6339 * PERFCOUNTER_CNT6_STATE enum
6342 typedef enum PERFCOUNTER_CNT6_STATE {
6350 * PERFCOUNTER_STATE_SEL6 enum
6353 typedef enum PERFCOUNTER_STATE_SEL6 {
6359 * PERFCOUNTER_CNT7_STATE enum
6362 typedef enum PERFCOUNTER_CNT7_STATE {
6370 * PERFCOUNTER_STATE_SEL7 enum
6373 typedef enum PERFCOUNTER_STATE_SEL7 {
6379 * PERFMON_STATE enum
6382 typedef enum PERFMON_STATE {
6390 * PERFMON_CNTOFF_AND_OR enum
6393 typedef enum PERFMON_CNTOFF_AND_OR {
6399 * PERFMON_CNTOFF_INT_EN enum
6402 typedef enum PERFMON_CNTOFF_INT_EN {
6408 * PERFMON_CNTOFF_INT_TYPE enum
6411 typedef enum PERFMON_CNTOFF_INT_TYPE {
6421 * SCL_C_RAM_TAP_PAIR_IDX enum
6424 typedef enum SCL_C_RAM_TAP_PAIR_IDX {
6433 * SCL_C_RAM_PHASE enum
6436 typedef enum SCL_C_RAM_PHASE {
6449 * SCL_C_RAM_FILTER_TYPE enum
6452 typedef enum SCL_C_RAM_FILTER_TYPE {
6460 * SCL_MODE_SEL enum
6463 typedef enum SCL_MODE_SEL {
6471 * SCL_PSCL_EN enum
6474 typedef enum SCL_PSCL_EN {
6480 * SCL_V_NUM_OF_TAPS enum
6483 typedef enum SCL_V_NUM_OF_TAPS {
6493 * SCL_H_NUM_OF_TAPS enum
6496 typedef enum SCL_H_NUM_OF_TAPS {
6506 * SCL_BOUNDARY_MODE enum
6509 typedef enum SCL_BOUNDARY_MODE {
6515 * SCL_EARLY_EOL_MOD enum
6518 typedef enum SCL_EARLY_EOL_MOD {
6524 * SCL_BYPASS_MODE enum
6527 typedef enum SCL_BYPASS_MODE {
6535 * SCL_V_MANUAL_REPLICATE_FACTOR enum
6538 typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
6558 * SCL_H_MANUAL_REPLICATE_FACTOR enum
6561 typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
6581 * SCL_V_CALC_AUTO_RATIO_EN enum
6584 typedef enum SCL_V_CALC_AUTO_RATIO_EN {
6590 * SCL_H_CALC_AUTO_RATIO_EN enum
6593 typedef enum SCL_H_CALC_AUTO_RATIO_EN {
6599 * SCL_H_FILTER_PICK_NEAREST enum
6602 typedef enum SCL_H_FILTER_PICK_NEAREST {
6608 * SCL_H_2TAP_HARDCODE_COEF_EN enum
6611 typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
6617 * SCL_V_FILTER_PICK_NEAREST enum
6620 typedef enum SCL_V_FILTER_PICK_NEAREST {
6626 * SCL_V_2TAP_HARDCODE_COEF_EN enum
6629 typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
6635 * SCL_UPDATE_TAKEN enum
6638 typedef enum SCL_UPDATE_TAKEN {
6644 * SCL_UPDATE_LOCK enum
6647 typedef enum SCL_UPDATE_LOCK {
6653 * SCL_COEF_UPDATE_COMPLETE enum
6656 typedef enum SCL_COEF_UPDATE_COMPLETE {
6662 * SCL_HF_SHARP_SCALE_FACTOR enum
6665 typedef enum SCL_HF_SHARP_SCALE_FACTOR {
6677 * SCL_HF_SHARP_EN enum
6680 typedef enum SCL_HF_SHARP_EN {
6686 * SCL_VF_SHARP_SCALE_FACTOR enum
6689 typedef enum SCL_VF_SHARP_SCALE_FACTOR {
6701 * SCL_VF_SHARP_EN enum
6704 typedef enum SCL_VF_SHARP_EN {
6710 * SCL_ALU_DISABLE enum
6713 typedef enum SCL_ALU_DISABLE {
6719 * SCL_HOST_CONFLICT_MASK enum
6722 typedef enum SCL_HOST_CONFLICT_MASK {
6728 * SCL_SCL_MODE_CHANGE_MASK enum
6731 typedef enum SCL_SCL_MODE_CHANGE_MASK {
6741 * SCLV_MODE_SEL enum
6744 typedef enum SCLV_MODE_SEL {
6752 * SCLV_INTERLACE_SOURCE enum
6755 typedef enum SCLV_INTERLACE_SOURCE {
6762 * SCLV_UPDATE_LOCK enum
6765 typedef enum SCLV_UPDATE_LOCK {
6771 * SCLV_COEF_UPDATE_COMPLETE enum
6774 typedef enum SCLV_COEF_UPDATE_COMPLETE {
6784 * DPRX_SD_PIXEL_ENCODING enum
6787 typedef enum DPRX_SD_PIXEL_ENCODING {
6795 * DPRX_SD_COMPONENT_DEPTH enum
6798 typedef enum DPRX_SD_COMPONENT_DEPTH {
6811 * AZ_LATENCY_COUNTER_CONTROL enum
6814 typedef enum AZ_LATENCY_COUNTER_CONTROL {
6824 * BLND_CONTROL_BLND_MODE enum
6827 typedef enum BLND_CONTROL_BLND_MODE {
6835 * BLND_CONTROL_BLND_STEREO_TYPE enum
6838 typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
6846 * BLND_CONTROL_BLND_STEREO_POLARITY enum
6849 typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
6855 * BLND_CONTROL_BLND_FEEDTHROUGH_EN enum
6858 typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
6864 * BLND_CONTROL_BLND_ALPHA_MODE enum
6867 typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
6875 * BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
6878 typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
6884 * BLND_CONTROL_BLND_MULTIPLIED_MODE enum
6887 typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
6893 * BLND_SM_CONTROL2_SM_MODE enum
6896 typedef enum BLND_SM_CONTROL2_SM_MODE {
6904 * BLND_SM_CONTROL2_SM_FRAME_ALTERNATE enum
6907 typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
6913 * BLND_SM_CONTROL2_SM_FIELD_ALTERNATE enum
6916 typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
6922 * BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
6925 typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
6933 * BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
6936 typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
6944 * BLND_CONTROL2_PTI_ENABLE enum
6947 typedef enum BLND_CONTROL2_PTI_ENABLE {
6953 * BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
6956 typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
6962 * BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
6965 typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
6971 * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
6974 typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
6980 * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
6983 typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
6989 * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
6992 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
6998 * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
7001 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
7007 * BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
7010 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
7016 * BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
7019 typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
7025 * BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
7028 typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
7034 * BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
7037 typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
7043 * BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
7046 typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
7052 * BLND_DEBUG_BLND_CNV_MUX_SELECT enum
7055 typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
7061 * BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
7064 typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
7074 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7077 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7091 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7094 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7100 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7103 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7109 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7112 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7118 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7121 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7127 … AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7130 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAP…
7136 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7139 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7145 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7148 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7154 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
7157 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7163 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7166 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVER…
7172 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7175 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT…
7181 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7184 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7190 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
7193 typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITI…
7199 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7202 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7216 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7219 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7225 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7228 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7234 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7237 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7243 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7246 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7252 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7255 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILIT…
7261 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7264 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7270 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7273 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7279 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7282 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7288 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7291 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7297 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7300 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7306 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
7309 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7315 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
7318 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7324 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
7327 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7333 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
7336 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7342 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
7345 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7351 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
7354 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7360 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
7363 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7369 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
7372 typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7378 * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
7381 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
7387 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
7390 typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7400 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7403 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7417 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7420 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7426 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7429 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7435 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7438 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7444 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7447 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7453 …A_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7456 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPON…
7462 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7465 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7471 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7474 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7480 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
7483 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7489 …ALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7492 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETE…
7498 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7501 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_P…
7507 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7510 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PR…
7516 …AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
7519 typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPA…
7525 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7528 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7542 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7545 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7551 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7554 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7560 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7563 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7569 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7572 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7578 … AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7581 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAP…
7587 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7590 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7596 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7599 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7605 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7608 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVER…
7614 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7617 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT…
7623 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7626 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7632 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
7635 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
7641 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
7644 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7650 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
7653 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
7659 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
7662 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7668 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
7671 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7677 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
7680 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7686 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
7689 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7695 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
7698 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7704 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
7707 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7713 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
7716 typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7722 * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
7725 typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7735 * UNP_GRPH_EN enum
7738 typedef enum UNP_GRPH_EN {
7744 * UNP_GRPH_DEPTH enum
7747 typedef enum UNP_GRPH_DEPTH {
7754 * UNP_GRPH_NUM_BANKS enum
7757 typedef enum UNP_GRPH_NUM_BANKS {
7765 * UNP_GRPH_BANK_WIDTH enum
7768 typedef enum UNP_GRPH_BANK_WIDTH {
7776 * UNP_GRPH_BANK_HEIGHT enum
7779 typedef enum UNP_GRPH_BANK_HEIGHT {
7787 * UNP_GRPH_TILE_SPLIT enum
7790 typedef enum UNP_GRPH_TILE_SPLIT {
7801 * UNP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
7804 typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
7810 * UNP_GRPH_MACRO_TILE_ASPECT enum
7813 typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
7821 * UNP_GRPH_COLOR_EXPANSION_MODE enum
7824 typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
7830 * UNP_VIDEO_FORMAT enum
7833 typedef enum UNP_VIDEO_FORMAT {
7845 * UNP_GRPH_ENDIAN_SWAP enum
7848 typedef enum UNP_GRPH_ENDIAN_SWAP {
7856 * UNP_GRPH_RED_CROSSBAR enum
7859 typedef enum UNP_GRPH_RED_CROSSBAR {
7867 * UNP_GRPH_GREEN_CROSSBAR enum
7870 typedef enum UNP_GRPH_GREEN_CROSSBAR {
7878 * UNP_GRPH_BLUE_CROSSBAR enum
7881 typedef enum UNP_GRPH_BLUE_CROSSBAR {
7889 * UNP_GRPH_MODE_UPDATE_LOCKG enum
7892 typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
7898 * UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
7901 typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
7907 * UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
7910 typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
7916 * UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
7919 typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
7925 * UNP_GRPH_STEREOSYNC_FLIP_EN enum
7928 typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
7934 * UNP_GRPH_STEREOSYNC_FLIP_MODE enum
7937 typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
7945 * UNP_GRPH_STACK_INTERLACE_FLIP_EN enum
7948 typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
7954 * UNP_GRPH_STACK_INTERLACE_FLIP_MODE enum
7957 typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
7965 * UNP_GRPH_STEREOSYNC_SELECT_DISABLE enum
7968 typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
7974 * UNP_CRC_SOURCE_SEL enum
7977 typedef enum UNP_CRC_SOURCE_SEL {
7986 * UNP_CRC_LINE_SEL enum
7989 typedef enum UNP_CRC_LINE_SEL {
7997 * UNP_ROTATION_ANGLE enum
8000 typedef enum UNP_ROTATION_ANGLE {
8012 * UNP_PIXEL_DROP enum
8015 typedef enum UNP_PIXEL_DROP {
8021 * UNP_BUFFER_MODE enum
8024 typedef enum UNP_BUFFER_MODE {
8034 * DP_LINK_TRAINING_COMPLETE enum
8037 typedef enum DP_LINK_TRAINING_COMPLETE {
8043 * DP_EMBEDDED_PANEL_MODE enum
8046 typedef enum DP_EMBEDDED_PANEL_MODE {
8052 * DP_PIXEL_ENCODING enum
8055 typedef enum DP_PIXEL_ENCODING {
8066 * DP_DYN_RANGE enum
8069 typedef enum DP_DYN_RANGE {
8075 * DP_YCBCR_RANGE enum
8078 typedef enum DP_YCBCR_RANGE {
8084 * DP_COMPONENT_DEPTH enum
8087 typedef enum DP_COMPONENT_DEPTH {
8097 * DP_MSA_MISC0_OVERRIDE_ENABLE enum
8100 typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
8106 * DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE enum
8109 typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE {
8115 * DP_UDI_LANES enum
8118 typedef enum DP_UDI_LANES {
8126 * DP_VID_STREAM_DIS_DEFER enum
8129 typedef enum DP_VID_STREAM_DIS_DEFER {
8136 * DP_STEER_OVERFLOW_ACK enum
8139 typedef enum DP_STEER_OVERFLOW_ACK {
8145 * DP_STEER_OVERFLOW_MASK enum
8148 typedef enum DP_STEER_OVERFLOW_MASK {
8154 * DP_TU_OVERFLOW_ACK enum
8157 typedef enum DP_TU_OVERFLOW_ACK {
8163 * DPHY_ALT_SCRAMBLER_RESET_EN enum
8166 typedef enum DPHY_ALT_SCRAMBLER_RESET_EN {
8172 * DPHY_ALT_SCRAMBLER_RESET_SEL enum
8175 typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL {
8181 * DP_VID_TIMING_MODE enum
8184 typedef enum DP_VID_TIMING_MODE {
8190 * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
8193 typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
8199 * DP_VID_M_N_GEN_EN enum
8202 typedef enum DP_VID_M_N_GEN_EN {
8208 * DP_VID_M_DOUBLE_VALUE_EN enum
8211 typedef enum DP_VID_M_DOUBLE_VALUE_EN {
8217 * DP_VID_ENHANCED_FRAME_MODE enum
8220 typedef enum DP_VID_ENHANCED_FRAME_MODE {
8226 * DP_VID_MSA_TOP_FIELD_MODE enum
8229 typedef enum DP_VID_MSA_TOP_FIELD_MODE {
8235 * DP_VID_VBID_FIELD_POL enum
8238 typedef enum DP_VID_VBID_FIELD_POL {
8244 * DP_VID_STREAM_DISABLE_ACK enum
8247 typedef enum DP_VID_STREAM_DISABLE_ACK {
8253 * DP_VID_STREAM_DISABLE_MASK enum
8256 typedef enum DP_VID_STREAM_DISABLE_MASK {
8262 * DPHY_ATEST_SEL_LANE0 enum
8265 typedef enum DPHY_ATEST_SEL_LANE0 {
8271 * DPHY_ATEST_SEL_LANE1 enum
8274 typedef enum DPHY_ATEST_SEL_LANE1 {
8280 * DPHY_ATEST_SEL_LANE2 enum
8283 typedef enum DPHY_ATEST_SEL_LANE2 {
8289 * DPHY_ATEST_SEL_LANE3 enum
8292 typedef enum DPHY_ATEST_SEL_LANE3 {
8298 * DPHY_SCRAMBLER_SEL enum
8301 typedef enum DPHY_SCRAMBLER_SEL {
8307 * DPHY_BYPASS enum
8310 typedef enum DPHY_BYPASS {
8316 * DPHY_SKEW_BYPASS enum
8319 typedef enum DPHY_SKEW_BYPASS {
8325 * DPHY_TRAINING_PATTERN_SEL enum
8328 typedef enum DPHY_TRAINING_PATTERN_SEL {
8336 * DPHY_8B10B_RESET enum
8339 typedef enum DPHY_8B10B_RESET {
8345 * DP_DPHY_8B10B_EXT_DISP enum
8348 typedef enum DP_DPHY_8B10B_EXT_DISP {
8354 * DPHY_8B10B_CUR_DISP enum
8357 typedef enum DPHY_8B10B_CUR_DISP {
8363 * DPHY_PRBS_EN enum
8366 typedef enum DPHY_PRBS_EN {
8372 * DPHY_PRBS_SEL enum
8375 typedef enum DPHY_PRBS_SEL {
8382 * DPHY_SCRAMBLER_DIS enum
8385 typedef enum DPHY_SCRAMBLER_DIS {
8391 * DPHY_SCRAMBLER_ADVANCE enum
8394 typedef enum DPHY_SCRAMBLER_ADVANCE {
8400 * DPHY_SCRAMBLER_KCODE enum
8403 typedef enum DPHY_SCRAMBLER_KCODE {
8409 * DPHY_LOAD_BS_COUNT_START enum
8412 typedef enum DPHY_LOAD_BS_COUNT_START {
8418 * DPHY_CRC_EN enum
8421 typedef enum DPHY_CRC_EN {
8427 * DPHY_CRC_CONT_EN enum
8430 typedef enum DPHY_CRC_CONT_EN {
8436 * DPHY_CRC_FIELD enum
8439 typedef enum DPHY_CRC_FIELD {
8445 * DPHY_CRC_SEL enum
8448 typedef enum DPHY_CRC_SEL {
8456 * DPHY_RX_FAST_TRAINING_CAPABLE enum
8459 typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
8465 * DP_SEC_COLLISION_ACK enum
8468 typedef enum DP_SEC_COLLISION_ACK {
8474 * DP_SEC_AUDIO_MUTE enum
8477 typedef enum DP_SEC_AUDIO_MUTE {
8483 * DP_SEC_TIMESTAMP_MODE enum
8486 typedef enum DP_SEC_TIMESTAMP_MODE {
8492 * DP_SEC_ASP_PRIORITY enum
8495 typedef enum DP_SEC_ASP_PRIORITY {
8501 * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
8504 typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
8510 * DP_MSE_SAT_UPDATE_ACT enum
8513 typedef enum DP_MSE_SAT_UPDATE_ACT {
8520 * DP_MSE_LINK_LINE enum
8523 typedef enum DP_MSE_LINK_LINE {
8531 * DP_MSE_BLANK_CODE enum
8534 typedef enum DP_MSE_BLANK_CODE {
8540 * DP_MSE_TIMESTAMP_MODE enum
8543 typedef enum DP_MSE_TIMESTAMP_MODE {
8549 * DP_MSE_ZERO_ENCODER enum
8552 typedef enum DP_MSE_ZERO_ENCODER {
8558 * DP_MSE_OUTPUT_DPDBG_DATA enum
8561 typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
8567 * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
8570 typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
8579 * DPHY_CRC_MST_PHASE_ERROR_ACK enum
8582 typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
8588 * DPHY_SW_FAST_TRAINING_START enum
8591 typedef enum DPHY_SW_FAST_TRAINING_START {
8597 * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
8600 typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
8606 * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
8609 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
8615 * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
8618 typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
8624 * DP_MSA_V_TIMING_OVERRIDE_EN enum
8627 typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
8633 * DP_SEC_GSP0_PRIORITY enum
8636 typedef enum DP_SEC_GSP0_PRIORITY {
8642 * DP_SEC_GSP0_SEND enum
8645 typedef enum DP_SEC_GSP0_SEND {
8655 * COL_MAN_UPDATE_LOCK enum
8658 typedef enum COL_MAN_UPDATE_LOCK {
8664 * COL_MAN_DISABLE_MULTIPLE_UPDATE enum
8667 typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
8673 * COL_MAN_INPUTCSC_MODE enum
8676 typedef enum COL_MAN_INPUTCSC_MODE {
8684 * COL_MAN_INPUTCSC_TYPE enum
8687 typedef enum COL_MAN_INPUTCSC_TYPE {
8694 * COL_MAN_INPUTCSC_CONVERT enum
8697 typedef enum COL_MAN_INPUTCSC_CONVERT {
8703 * COL_MAN_PRESCALE_MODE enum
8706 typedef enum COL_MAN_PRESCALE_MODE {
8713 * COL_MAN_INPUT_GAMMA_MODE enum
8716 typedef enum COL_MAN_INPUT_GAMMA_MODE {
8723 * COL_MAN_OUTPUT_CSC_MODE enum
8726 typedef enum COL_MAN_OUTPUT_CSC_MODE {
8737 * COL_MAN_DENORM_CLAMP_CONTROL enum
8740 typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
8748 * COL_MAN_REGAMMA_MODE_CONTROL enum
8751 typedef enum COL_MAN_REGAMMA_MODE_CONTROL {
8760 * COL_MAN_GLOBAL_PASSTHROUGH_ENABLE enum
8763 typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
8769 * COL_MAN_DEGAMMA_MODE enum
8772 typedef enum COL_MAN_DEGAMMA_MODE {
8779 * COL_MAN_GAMUT_REMAP_MODE enum
8782 typedef enum COL_MAN_GAMUT_REMAP_MODE {
8798 * DP_AUX_CONTROL_HPD_SEL enum
8801 typedef enum DP_AUX_CONTROL_HPD_SEL {
8811 * DP_AUX_CONTROL_TEST_MODE enum
8814 typedef enum DP_AUX_CONTROL_TEST_MODE {
8820 * DP_AUX_SW_CONTROL_SW_GO enum
8823 typedef enum DP_AUX_SW_CONTROL_SW_GO {
8829 * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
8832 typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
8838 * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
8841 typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
8849 * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
8852 typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
8858 * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
8861 typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
8867 * DP_AUX_INT_ACK enum
8870 typedef enum DP_AUX_INT_ACK {
8876 * DP_AUX_LS_UPDATE_ACK enum
8879 typedef enum DP_AUX_LS_UPDATE_ACK {
8885 * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
8888 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
8894 * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
8897 typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
8905 * DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN enum
8908 typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
8920 * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
8923 typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
8933 * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
8936 typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
8948 * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
8951 typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
8963 * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
8966 typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
8974 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
8977 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
8983 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
8986 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
8992 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
8995 typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
9001 * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
9004 typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
9012 * DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN enum
9015 typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
9027 * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
9030 typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
9042 * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
9045 typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
9051 * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
9054 typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
9062 * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
9065 typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
9073 * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
9076 typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
9084 * DP_AUX_ERR_OCCURRED_ACK enum
9087 typedef enum DP_AUX_ERR_OCCURRED_ACK {
9093 * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
9096 typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
9102 * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
9105 typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
9111 * DP_AUX_RESET enum
9114 typedef enum DP_AUX_RESET {
9120 * DP_AUX_RESET_DONE enum
9123 typedef enum DP_AUX_RESET_DONE {
9133 * DSI_COMMAND_MODE_SRC_FORMAT enum
9136 typedef enum DSI_COMMAND_MODE_SRC_FORMAT {
9146 * DSI_COMMAND_MODE_DST_FORMAT enum
9149 typedef enum DSI_COMMAND_MODE_DST_FORMAT {
9159 * DSI_FLAG_CLR enum
9162 typedef enum DSI_FLAG_CLR {
9168 * DSI_BIT_SWAP enum
9171 typedef enum DSI_BIT_SWAP {
9177 * DSI_CLK_GATING enum
9180 typedef enum DSI_CLK_GATING {
9186 * DSI_LANE_ULPS_REQUEST enum
9189 typedef enum DSI_LANE_ULPS_REQUEST {
9195 * DSI_LANE_ULPS_EXIT enum
9198 typedef enum DSI_LANE_ULPS_EXIT {
9204 * DSI_LANE_FORCE_TX_STOP enum
9207 typedef enum DSI_LANE_FORCE_TX_STOP {
9213 * DSI_CLOCK_LANE_HS_FORCE_REQUEST enum
9216 typedef enum DSI_CLOCK_LANE_HS_FORCE_REQUEST {
9222 * DSI_CONTROLLER_EN enum
9225 typedef enum DSI_CONTROLLER_EN {
9231 * DSI_VIDEO_MODE_EN enum
9234 typedef enum DSI_VIDEO_MODE_EN {
9240 * DSI_CMD_MODE_EN enum
9243 typedef enum DSI_CMD_MODE_EN {
9249 * DSI_DATA_LANE0_EN enum
9252 typedef enum DSI_DATA_LANE0_EN {
9258 * DSI_DATA_LANE1_EN enum
9261 typedef enum DSI_DATA_LANE1_EN {
9267 * DSI_DATA_LANE2_EN enum
9270 typedef enum DSI_DATA_LANE2_EN {
9276 * DSI_DATA_LANE3_EN enum
9279 typedef enum DSI_DATA_LANE3_EN {
9285 * DSI_CLOCK_LANE_EN enum
9288 typedef enum DSI_CLOCK_LANE_EN {
9294 * DSI_PHY_DATA_LANE0_EN enum
9297 typedef enum DSI_PHY_DATA_LANE0_EN {
9303 * DSI_PHY_DATA_LANE1_EN enum
9306 typedef enum DSI_PHY_DATA_LANE1_EN {
9312 * DSI_PHY_DATA_LANE2_EN enum
9315 typedef enum DSI_PHY_DATA_LANE2_EN {
9321 * DSI_PHY_DATA_LANE3_EN enum
9324 typedef enum DSI_PHY_DATA_LANE3_EN {
9330 * DSI_RESET_DISPCLK enum
9333 typedef enum DSI_RESET_DISPCLK {
9339 * DSI_RESET_DSICLK enum
9342 typedef enum DSI_RESET_DSICLK {
9348 * DSI_RESET_BYTECLK enum
9351 typedef enum DSI_RESET_BYTECLK {
9357 * DSI_RESET_ESCCLK enum
9360 typedef enum DSI_RESET_ESCCLK {
9366 * DSI_CRTC_SEL enum
9369 typedef enum DSI_CRTC_SEL {
9379 * DSI_PACKET_BYTE_MSB_LSB_FLIP enum
9382 typedef enum DSI_PACKET_BYTE_MSB_LSB_FLIP {
9388 * DSI_VIDEO_MODE_DST_FORMAT enum
9391 typedef enum DSI_VIDEO_MODE_DST_FORMAT {
9399 * DSI_VIDEO_TRAFFIC_MODE enum
9402 typedef enum DSI_VIDEO_TRAFFIC_MODE {
9410 * DSI_VIDEO_BLLP_PWR_MODE enum
9413 typedef enum DSI_VIDEO_BLLP_PWR_MODE {
9419 * DSI_VIDEO_EOF_BLLP_PWR_MODE enum
9422 typedef enum DSI_VIDEO_EOF_BLLP_PWR_MODE {
9428 * DSI_VIDEO_PWR_MODE enum
9431 typedef enum DSI_VIDEO_PWR_MODE {
9437 * DSI_VIDEO_PULSE_MODE_OPT enum
9440 typedef enum DSI_VIDEO_PULSE_MODE_OPT {
9446 * DSI_RGB_SWAP enum
9449 typedef enum DSI_RGB_SWAP {
9459 * DSI_CMD_PACKET_TYPE enum
9462 typedef enum DSI_CMD_PACKET_TYPE {
9468 * DSI_CMD_PWR_MODE enum
9471 typedef enum DSI_CMD_PWR_MODE {
9477 * DSI_CMD_EMBEDDED_MODE enum
9480 typedef enum DSI_CMD_EMBEDDED_MODE {
9486 * DSI_CMD_ORDER enum
9489 typedef enum DSI_CMD_ORDER {
9495 * DSI_DATA_BUFFER_ID enum
9498 typedef enum DSI_DATA_BUFFER_ID {
9504 * DSI_DWORD_BYTE_SWAP enum
9507 typedef enum DSI_DWORD_BYTE_SWAP {
9515 * DSI_INSERT_DCS_COMMAND enum
9518 typedef enum DSI_INSERT_DCS_COMMAND {
9524 * DSI_DMAFIFO_WRITE_WATERMARK enum
9527 typedef enum DSI_DMAFIFO_WRITE_WATERMARK {
9535 * DSI_DMAFIFO_READ_WATERMARK enum
9538 typedef enum DSI_DMAFIFO_READ_WATERMARK {
9546 * DSI_USE_DENG_LENGTH enum
9549 typedef enum DSI_USE_DENG_LENGTH {
9555 * DSI_COMMAND_TRIGGER_MODE enum
9558 typedef enum DSI_COMMAND_TRIGGER_MODE {
9564 * DSI_COMMAND_TRIGGER_SEL enum
9567 typedef enum DSI_COMMAND_TRIGGER_SEL {
9575 * DSI_HW_SOURCE_SEL enum
9578 typedef enum DSI_HW_SOURCE_SEL {
9586 * DSI_COMMAND_TRIGGER_ORDER enum
9589 typedef enum DSI_COMMAND_TRIGGER_ORDER {
9595 * DSI_TE_SRC_SEL enum
9598 typedef enum DSI_TE_SRC_SEL {
9604 * DSI_EXT_TE_MUX enum
9607 typedef enum DSI_EXT_TE_MUX {
9620 * DSI_EXT_TE_MODE enum
9623 typedef enum DSI_EXT_TE_MODE {
9631 * DSI_EXT_RESET_POL enum
9634 typedef enum DSI_EXT_RESET_POL {
9640 * DSI_EXT_TE_POL enum
9643 typedef enum DSI_EXT_TE_POL {
9649 * DSI_RESET_PANEL enum
9652 typedef enum DSI_RESET_PANEL {
9658 * DSI_CRC_ENABLE enum
9661 typedef enum DSI_CRC_ENABLE {
9667 * DSI_TX_EOT_APPEND enum
9670 typedef enum DSI_TX_EOT_APPEND {
9676 * DSI_RX_EOT_IGNORE enum
9679 typedef enum DSI_RX_EOT_IGNORE {
9685 * DSI_MIPI_BIST_RESET enum
9688 typedef enum DSI_MIPI_BIST_RESET {
9694 * DSI_MIPI_BIST_VIDEO_FRMT enum
9697 typedef enum DSI_MIPI_BIST_VIDEO_FRMT {
9703 * DSI_MIPI_BIST_START enum
9706 typedef enum DSI_MIPI_BIST_START {
9712 * DSI_DBG_CLK_SEL enum
9715 typedef enum DSI_DBG_CLK_SEL {
9728 * DSI_DENG_FIFO_USE_OVERWRITE_LEVEL enum
9731 typedef enum DSI_DENG_FIFO_USE_OVERWRITE_LEVEL {
9737 * DSI_DENG_FIFO_FORCE_RECAL_AVERAGE enum
9740 typedef enum DSI_DENG_FIFO_FORCE_RECAL_AVERAGE {
9746 * DSI_DENG_FIFO_FORCE_RECOMP_MINMAX enum
9749 typedef enum DSI_DENG_FIFO_FORCE_RECOMP_MINMAX {
9755 * DSI_DENG_FIFO_START enum
9758 typedef enum DSI_DENG_FIFO_START {
9764 * DSI_USE_CMDFIFO enum
9767 typedef enum DSI_USE_CMDFIFO {
9773 * DSI_CRTC_FREEZE_TRIG enum
9776 typedef enum DSI_CRTC_FREEZE_TRIG {
9782 * DSI_PERF_LATENCY_SEL enum
9785 typedef enum DSI_PERF_LATENCY_SEL {
9793 * DSI_DEBUG_DSICLK_SEL enum
9796 typedef enum DSI_DEBUG_DSICLK_SEL {
9807 * DSI_DEBUG_BYTECLK_SEL enum
9810 typedef enum DSI_DEBUG_BYTECLK_SEL {
9833 * DCIOCHIP_HPD_SEL enum
9836 typedef enum DCIOCHIP_HPD_SEL {
9842 * DCIOCHIP_PAD_MODE enum
9845 typedef enum DCIOCHIP_PAD_MODE {
9851 * DCIOCHIP_AUXSLAVE_PAD_MODE enum
9854 typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
9860 * DCIOCHIP_INVERT enum
9863 typedef enum DCIOCHIP_INVERT {
9869 * DCIOCHIP_PD_EN enum
9872 typedef enum DCIOCHIP_PD_EN {
9878 * DCIOCHIP_GPIO_MASK_EN enum
9881 typedef enum DCIOCHIP_GPIO_MASK_EN {
9887 * DCIOCHIP_MASK enum
9890 typedef enum DCIOCHIP_MASK {
9896 * DCIOCHIP_GPIO_I2C_MASK enum
9899 typedef enum DCIOCHIP_GPIO_I2C_MASK {
9905 * DCIOCHIP_GPIO_I2C_DRIVE enum
9908 typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
9914 * DCIOCHIP_GPIO_I2C_EN enum
9917 typedef enum DCIOCHIP_GPIO_I2C_EN {
9923 * DCIOCHIP_MASK_4BIT enum
9926 typedef enum DCIOCHIP_MASK_4BIT {
9932 * DCIOCHIP_ENABLE_4BIT enum
9935 typedef enum DCIOCHIP_ENABLE_4BIT {
9941 * DCIOCHIP_MASK_5BIT enum
9944 typedef enum DCIOCHIP_MASK_5BIT {
9950 * DCIOCHIP_ENABLE_5BIT enum
9953 typedef enum DCIOCHIP_ENABLE_5BIT {
9959 * DCIOCHIP_MASK_2BIT enum
9962 typedef enum DCIOCHIP_MASK_2BIT {
9968 * DCIOCHIP_ENABLE_2BIT enum
9971 typedef enum DCIOCHIP_ENABLE_2BIT {
9977 * DCIOCHIP_REF_27_SRC_SEL enum
9980 typedef enum DCIOCHIP_REF_27_SRC_SEL {
9988 * DCIOCHIP_DVO_VREFPON enum
9991 typedef enum DCIOCHIP_DVO_VREFPON {
9997 * DCIOCHIP_DVO_VREFSEL enum
10000 typedef enum DCIOCHIP_DVO_VREFSEL {
10006 * DCIOCHIP_SPDIF1_IMODE enum
10009 typedef enum DCIOCHIP_SPDIF1_IMODE {
10015 * DCIOCHIP_AUX_FALLSLEWSEL enum
10018 typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
10026 * DCIOCHIP_AUX_SPIKESEL enum
10029 typedef enum DCIOCHIP_AUX_SPIKESEL {
10035 * DCIOCHIP_AUX_CSEL0P9 enum
10038 typedef enum DCIOCHIP_AUX_CSEL0P9 {
10044 * DCIOCHIP_AUX_CSEL1P1 enum
10047 typedef enum DCIOCHIP_AUX_CSEL1P1 {
10053 * DCIOCHIP_AUX_RSEL0P9 enum
10056 typedef enum DCIOCHIP_AUX_RSEL0P9 {
10062 * DCIOCHIP_AUX_RSEL1P1 enum
10065 typedef enum DCIOCHIP_AUX_RSEL1P1 {
10075 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
10078 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
10084 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
10087 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
10093 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
10096 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
10102 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
10105 typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
10111 * AZ_GLOBAL_CAPABILITIES enum
10114 typedef enum AZ_GLOBAL_CAPABILITIES {
10120 * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
10123 typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
10129 * GLOBAL_CONTROL_FLUSH_CONTROL enum
10132 typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
10138 * GLOBAL_CONTROL_CONTROLLER_RESET enum
10141 typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
10147 * AZ_STATE_CHANGE_STATUS enum
10150 typedef enum AZ_STATE_CHANGE_STATUS {
10156 * GLOBAL_STATUS_FLUSH_STATUS enum
10159 typedef enum GLOBAL_STATUS_FLUSH_STATUS {
10165 * STREAM_0_SYNCHRONIZATION enum
10168 typedef enum STREAM_0_SYNCHRONIZATION {
10174 * STREAM_1_SYNCHRONIZATION enum
10177 typedef enum STREAM_1_SYNCHRONIZATION {
10183 * STREAM_2_SYNCHRONIZATION enum
10186 typedef enum STREAM_2_SYNCHRONIZATION {
10192 * STREAM_3_SYNCHRONIZATION enum
10195 typedef enum STREAM_3_SYNCHRONIZATION {
10201 * STREAM_4_SYNCHRONIZATION enum
10204 typedef enum STREAM_4_SYNCHRONIZATION {
10210 * STREAM_5_SYNCHRONIZATION enum
10213 typedef enum STREAM_5_SYNCHRONIZATION {
10219 * STREAM_6_SYNCHRONIZATION enum
10222 typedef enum STREAM_6_SYNCHRONIZATION {
10228 * STREAM_7_SYNCHRONIZATION enum
10231 typedef enum STREAM_7_SYNCHRONIZATION {
10237 * STREAM_8_SYNCHRONIZATION enum
10240 typedef enum STREAM_8_SYNCHRONIZATION {
10246 * STREAM_9_SYNCHRONIZATION enum
10249 typedef enum STREAM_9_SYNCHRONIZATION {
10255 * STREAM_10_SYNCHRONIZATION enum
10258 typedef enum STREAM_10_SYNCHRONIZATION {
10264 * STREAM_11_SYNCHRONIZATION enum
10267 typedef enum STREAM_11_SYNCHRONIZATION {
10273 * STREAM_12_SYNCHRONIZATION enum
10276 typedef enum STREAM_12_SYNCHRONIZATION {
10282 * STREAM_13_SYNCHRONIZATION enum
10285 typedef enum STREAM_13_SYNCHRONIZATION {
10291 * STREAM_14_SYNCHRONIZATION enum
10294 typedef enum STREAM_14_SYNCHRONIZATION {
10300 * STREAM_15_SYNCHRONIZATION enum
10303 typedef enum STREAM_15_SYNCHRONIZATION {
10309 * CORB_READ_POINTER_RESET enum
10312 typedef enum CORB_READ_POINTER_RESET {
10318 * AZ_CORB_SIZE enum
10321 typedef enum AZ_CORB_SIZE {
10329 * AZ_RIRB_WRITE_POINTER_RESET enum
10332 typedef enum AZ_RIRB_WRITE_POINTER_RESET {
10338 * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
10341 typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
10347 * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
10350 typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
10356 * AZ_RIRB_SIZE enum
10359 typedef enum AZ_RIRB_SIZE {
10367 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
10370 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
10376 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
10379 typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
10385 * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
10388 typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
10398 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10401 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10407 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10410 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10416 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10419 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10428 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10431 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10443 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10446 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10456 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10459 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10472 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
10475 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
10481 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
10484 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
10490 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
10493 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
10499 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
10502 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
10508 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
10511 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
10517 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
10520 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
10526 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
10529 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
10535 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10538 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10544 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
10547 typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
10553 * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
10556 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
10562 * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10565 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10571 * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
10574 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
10580 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
10583 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
10589 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
10592 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
10598 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
10601 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
10607 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
10610 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
10616 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10619 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10625 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10628 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10634 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10637 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10643 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10646 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10652 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10655 typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10665 * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
10668 typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
10678 * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
10681 typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
10693 * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
10696 typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
10712 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10715 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10721 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10724 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10730 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10733 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10742 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10745 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10757 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10760 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10770 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10773 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10786 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10789 typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10795 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
10798 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
10804 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10807 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10813 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
10816 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
10822 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10825 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10831 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
10834 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
10840 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10843 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10849 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
10852 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
10858 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10861 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10867 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
10870 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
10876 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10879 typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10889 * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
10892 typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
10902 * ENABLE enum
10905 typedef enum ENABLE {
10911 * ENABLE_CLOCK enum
10914 typedef enum ENABLE_CLOCK {
10920 * FORCE_VBI enum
10923 typedef enum FORCE_VBI {
10929 * OVERRIDE_CGTT_SCLK enum
10932 typedef enum OVERRIDE_CGTT_SCLK {
10938 * CLEAR_SMU_INTR enum
10941 typedef enum CLEAR_SMU_INTR {
10947 * STATIC_SCREEN_SMU_INTR enum
10950 typedef enum STATIC_SCREEN_SMU_INTR {
10956 * JITTER_REMOVE_DISABLE enum
10959 typedef enum JITTER_REMOVE_DISABLE {
10965 * DS_REF_SRC enum
10968 typedef enum DS_REF_SRC {
10975 * DISABLE_CLOCK_GATING enum
10978 typedef enum DISABLE_CLOCK_GATING {
10984 * DISABLE_CLOCK_GATING_IN_DCO enum
10987 typedef enum DISABLE_CLOCK_GATING_IN_DCO {
10993 * DCCG_DEEP_COLOR_CNTL enum
10996 typedef enum DCCG_DEEP_COLOR_CNTL {
11004 * REFCLK_CLOCK_EN enum
11007 typedef enum REFCLK_CLOCK_EN {
11013 * REFCLK_SRC_SEL enum
11016 typedef enum REFCLK_SRC_SEL {
11022 * DPREFCLK_SRC_SEL enum
11025 typedef enum DPREFCLK_SRC_SEL {
11034 * XTAL_REF_SEL enum
11037 typedef enum XTAL_REF_SEL {
11043 * XTAL_REF_CLOCK_SOURCE_SEL enum
11046 typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
11052 * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
11055 typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11061 * ALLOW_SR_ON_TRANS_REQ enum
11064 typedef enum ALLOW_SR_ON_TRANS_REQ {
11070 * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
11073 typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11079 * PIPE_PIXEL_RATE_SOURCE enum
11082 typedef enum PIPE_PIXEL_RATE_SOURCE {
11089 * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
11092 typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
11103 * PIPE_PIXEL_RATE_PLL_SOURCE enum
11106 typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
11112 * DP_DTO_DS_DISABLE enum
11115 typedef enum DP_DTO_DS_DISABLE {
11121 * CRTC_ADD_PIXEL enum
11124 typedef enum CRTC_ADD_PIXEL {
11130 * CRTC_DROP_PIXEL enum
11133 typedef enum CRTC_DROP_PIXEL {
11139 * SYMCLK_FE_FORCE_EN enum
11142 typedef enum SYMCLK_FE_FORCE_EN {
11148 * SYMCLK_FE_FORCE_SRC enum
11151 typedef enum SYMCLK_FE_FORCE_SRC {
11162 * DPDBG_CLK_FORCE_EN enum
11165 typedef enum DPDBG_CLK_FORCE_EN {
11171 * DVOACLK_COARSE_SKEW_CNTL enum
11174 typedef enum DVOACLK_COARSE_SKEW_CNTL {
11209 * DVOACLK_FINE_SKEW_CNTL enum
11212 typedef enum DVOACLK_FINE_SKEW_CNTL {
11224 * DVOACLKD_IN_PHASE enum
11227 typedef enum DVOACLKD_IN_PHASE {
11233 * DVOACLKC_IN_PHASE enum
11236 typedef enum DVOACLKC_IN_PHASE {
11242 * DVOACLKC_MVP_IN_PHASE enum
11245 typedef enum DVOACLKC_MVP_IN_PHASE {
11251 * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
11254 typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
11260 * MVP_CLK_SRC_SEL enum
11263 typedef enum MVP_CLK_SRC_SEL {
11271 * DCCG_AUDIO_DTO0_SOURCE_SEL enum
11274 typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
11285 * DCCG_AUDIO_DTO_SEL enum
11288 typedef enum DCCG_AUDIO_DTO_SEL {
11295 * DCCG_AUDIO_DTO2_SOURCE_SEL enum
11298 typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
11304 * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
11307 typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
11313 * DCCG_DBG_EN enum
11316 typedef enum DCCG_DBG_EN {
11322 * DCCG_DBG_BLOCK_SEL enum
11325 typedef enum DCCG_DBG_BLOCK_SEL {
11332 * DISPCLK_FREQ_RAMP_DONE enum
11335 typedef enum DISPCLK_FREQ_RAMP_DONE {
11341 * DCCG_FIFO_ERRDET_RESET enum
11344 typedef enum DCCG_FIFO_ERRDET_RESET {
11350 * DCCG_FIFO_ERRDET_STATE enum
11353 typedef enum DCCG_FIFO_ERRDET_STATE {
11359 * DCCG_FIFO_ERRDET_OVR_EN enum
11362 typedef enum DCCG_FIFO_ERRDET_OVR_EN {
11368 * DISPCLK_CHG_FWD_CORR_DISABLE enum
11371 typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
11377 * DC_MEM_GLOBAL_PWR_REQ_DIS enum
11380 typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
11386 * DCCG_PERF_RUN enum
11389 typedef enum DCCG_PERF_RUN {
11395 * DCCG_PERF_MODE_VSYNC enum
11398 typedef enum DCCG_PERF_MODE_VSYNC {
11404 * DCCG_PERF_MODE_HSYNC enum
11407 typedef enum DCCG_PERF_MODE_HSYNC {
11413 * DCCG_PERF_CRTC_SELECT enum
11416 typedef enum DCCG_PERF_CRTC_SELECT {
11426 * CLOCK_BRANCH_SOFT_RESET enum
11429 typedef enum CLOCK_BRANCH_SOFT_RESET {
11435 * PLL_CFG_IF_SOFT_RESET enum
11438 typedef enum PLL_CFG_IF_SOFT_RESET {
11444 * DVO_ENABLE_RST enum
11447 typedef enum DVO_ENABLE_RST {
11457 * LptNumPipes enum
11460 typedef enum LptNumPipes {
11468 * LptNumBanks enum
11471 typedef enum LptNumBanks {
11480 * OVERRIDE_CGTT_DCEFCLK enum
11483 typedef enum OVERRIDE_CGTT_DCEFCLK {
11493 * DCIO_DC_GENERICA_SEL enum
11496 typedef enum DCIO_DC_GENERICA_SEL {
11518 * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
11521 typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
11534 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
11537 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
11550 * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
11553 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
11566 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
11569 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
11582 * DCIO_DC_GENERICB_SEL enum
11585 typedef enum DCIO_DC_GENERICB_SEL {
11605 * DCIO_DC_PAD_EXTERN_SIG_SEL enum
11608 typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
11628 * DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS enum
11631 typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
11639 * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
11642 typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
11650 * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
11653 typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
11661 * DCIO_DC_GPIO_VIP_DEBUG enum
11664 typedef enum DCIO_DC_GPIO_VIP_DEBUG {
11670 * DCIO_DC_GPIO_MACRO_DEBUG enum
11673 typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
11681 * DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL enum
11684 typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
11690 * DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN enum
11693 typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
11699 * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum
11702 typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
11708 * DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum
11711 typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
11723 * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
11726 typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
11732 * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
11735 typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
11743 * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
11746 typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
11754 * DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum
11757 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
11763 * DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum
11766 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
11772 * DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum
11775 typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
11781 * DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum
11784 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
11790 * DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum
11793 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
11799 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum
11802 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
11808 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum
11811 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
11817 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum
11820 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
11826 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum
11829 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
11835 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum
11838 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
11844 * DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum
11847 typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
11853 * DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
11856 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
11862 * DCIO_BL_PWM_CNTL_BL_PWM_EN enum
11865 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
11871 * DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum
11874 typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
11882 * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
11885 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
11891 * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum
11894 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
11900 * DCIO_BL_PWM_GRP1_REG_LOCK enum
11903 typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
11909 * DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
11912 typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
11918 * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
11921 typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
11931 * DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
11934 typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
11940 * DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
11943 typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
11949 * DCIO_GSL_SEL enum
11952 typedef enum DCIO_GSL_SEL {
11959 * DCIO_GENLK_CLK_GSL_MASK enum
11962 typedef enum DCIO_GENLK_CLK_GSL_MASK {
11969 * DCIO_GENLK_VSYNC_GSL_MASK enum
11972 typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
11979 * DCIO_SWAPLOCK_A_GSL_MASK enum
11982 typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
11989 * DCIO_SWAPLOCK_B_GSL_MASK enum
11992 typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
11999 * DCIO_GSL_VSYNC_SEL enum
12002 typedef enum DCIO_GSL_VSYNC_SEL {
12012 * DCIO_GSL0_TIMING_SYNC_SEL enum
12015 typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
12024 * DCIO_GSL0_GLOBAL_UNLOCK_SEL enum
12027 typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
12036 * DCIO_GSL1_TIMING_SYNC_SEL enum
12039 typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
12048 * DCIO_GSL1_GLOBAL_UNLOCK_SEL enum
12051 typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
12060 * DCIO_GSL2_TIMING_SYNC_SEL enum
12063 typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
12072 * DCIO_GSL2_GLOBAL_UNLOCK_SEL enum
12075 typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
12084 * DCIO_DC_GPU_TIMER_START_POSITION enum
12087 typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
12099 * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
12102 typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
12109 * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
12112 typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
12118 * DCIO_DCO_DCFE_EXT_VSYNC_MUX enum
12121 typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
12133 * DCIO_DCO_EXT_VSYNC_MASK enum
12136 typedef enum DCIO_DCO_EXT_VSYNC_MASK {
12148 * DCIO_DSYNC_SOFT_RESET enum
12151 typedef enum DCIO_DSYNC_SOFT_RESET {
12157 * DCIO_DACA_SOFT_RESET enum
12160 typedef enum DCIO_DACA_SOFT_RESET {
12166 * DCIO_DCRXPHY_SOFT_RESET enum
12169 typedef enum DCIO_DCRXPHY_SOFT_RESET {
12175 * DCIO_DPHY_LANE_SEL enum
12178 typedef enum DCIO_DPHY_LANE_SEL {
12186 * DCIO_DPCS_INTERRUPT_TYPE enum
12189 typedef enum DCIO_DPCS_INTERRUPT_TYPE {
12195 * DCIO_DPCS_INTERRUPT_MASK enum
12198 typedef enum DCIO_DPCS_INTERRUPT_MASK {
12204 * DCIO_DC_GPU_TIMER_READ_SELECT enum
12207 typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
12247 * DCIO_IMPCAL_STEP_DELAY enum
12250 typedef enum DCIO_IMPCAL_STEP_DELAY {
12270 * DCIO_UNIPHY_IMPCAL_SEL enum
12273 typedef enum DCIO_UNIPHY_IMPCAL_SEL {
12279 * DCIO_DBG_ASYNC_BLOCK_SEL enum
12282 typedef enum DCIO_DBG_ASYNC_BLOCK_SEL {
12290 * DCIO_DBG_ASYNC_4BIT_SEL enum
12293 typedef enum DCIO_DBG_ASYNC_4BIT_SEL {
12309 * AOUT_EN enum
12312 typedef enum AOUT_EN {
12318 * AOUT_FIFO_START_ADDR enum
12321 typedef enum AOUT_FIFO_START_ADDR {
12327 * AOUT_CRC_TEST_EN enum
12330 typedef enum AOUT_CRC_TEST_EN {
12336 * AOUT_CRC_SOFT_RESET enum
12339 typedef enum AOUT_CRC_SOFT_RESET {
12345 * AOUT_CRC_CONT_EN enum
12348 typedef enum AOUT_CRC_CONT_EN {
12354 * I2S_WORD_SIZE enum
12357 typedef enum I2S_WORD_SIZE {
12363 * I2S_SAMPLE_ALIGNMENT enum
12366 typedef enum I2S_SAMPLE_ALIGNMENT {
12372 * I2S_SAMPLE_BIT_ORDER enum
12375 typedef enum I2S_SAMPLE_BIT_ORDER {
12381 * I2S_LRCLK_POLARITY enum
12384 typedef enum I2S_LRCLK_POLARITY {
12390 * I2S_WORD_ALIGNMENT enum
12393 typedef enum I2S_WORD_ALIGNMENT {
12399 * SPDIF_INVERT_EN enum
12402 typedef enum SPDIF_INVERT_EN {
12412 * DPDBG_EN enum
12415 typedef enum DPDBG_EN {
12421 * DPDBG_INPUT_EN enum
12424 typedef enum DPDBG_INPUT_EN {
12430 * DPDBG_ERROR_DETECTION_MODE enum
12433 typedef enum DPDBG_ERROR_DETECTION_MODE {
12439 * DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK enum
12442 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
12448 * DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE enum
12451 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
12457 * DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK enum
12460 typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
12466 * PM_ASSERT_RESET enum
12469 typedef enum PM_ASSERT_RESET {
12475 * DAC_MUX_SELECT enum
12478 typedef enum DAC_MUX_SELECT {
12484 * TMDS_DVO_MUX_SELECT enum
12487 typedef enum TMDS_DVO_MUX_SELECT {
12495 * DACA_SOFT_RESET enum
12498 typedef enum DACA_SOFT_RESET {
12504 * I2S0_SPDIF0_SOFT_RESET enum
12507 typedef enum I2S0_SPDIF0_SOFT_RESET {
12513 * I2S1_SOFT_RESET enum
12516 typedef enum I2S1_SOFT_RESET {
12522 * SPDIF1_SOFT_RESET enum
12525 typedef enum SPDIF1_SOFT_RESET {
12531 * DB_CLK_SOFT_RESET enum
12534 typedef enum DB_CLK_SOFT_RESET {
12540 * FMT0_SOFT_RESET enum
12543 typedef enum FMT0_SOFT_RESET {
12549 * FMT1_SOFT_RESET enum
12552 typedef enum FMT1_SOFT_RESET {
12558 * FMT2_SOFT_RESET enum
12561 typedef enum FMT2_SOFT_RESET {
12567 * FMT3_SOFT_RESET enum
12570 typedef enum FMT3_SOFT_RESET {
12576 * FMT4_SOFT_RESET enum
12579 typedef enum FMT4_SOFT_RESET {
12585 * FMT5_SOFT_RESET enum
12588 typedef enum FMT5_SOFT_RESET {
12594 * MVP_SOFT_RESET enum
12597 typedef enum MVP_SOFT_RESET {
12603 * ABM_SOFT_RESET enum
12606 typedef enum ABM_SOFT_RESET {
12612 * DVO_SOFT_RESET enum
12615 typedef enum DVO_SOFT_RESET {
12621 * DIGA_FE_SOFT_RESET enum
12624 typedef enum DIGA_FE_SOFT_RESET {
12630 * DIGA_BE_SOFT_RESET enum
12633 typedef enum DIGA_BE_SOFT_RESET {
12639 * DIGB_FE_SOFT_RESET enum
12642 typedef enum DIGB_FE_SOFT_RESET {
12648 * DIGB_BE_SOFT_RESET enum
12651 typedef enum DIGB_BE_SOFT_RESET {
12657 * DIGC_FE_SOFT_RESET enum
12660 typedef enum DIGC_FE_SOFT_RESET {
12666 * DIGC_BE_SOFT_RESET enum
12669 typedef enum DIGC_BE_SOFT_RESET {
12675 * DIGD_FE_SOFT_RESET enum
12678 typedef enum DIGD_FE_SOFT_RESET {
12684 * DIGD_BE_SOFT_RESET enum
12687 typedef enum DIGD_BE_SOFT_RESET {
12693 * DIGE_FE_SOFT_RESET enum
12696 typedef enum DIGE_FE_SOFT_RESET {
12702 * DIGE_BE_SOFT_RESET enum
12705 typedef enum DIGE_BE_SOFT_RESET {
12711 * DIGF_FE_SOFT_RESET enum
12714 typedef enum DIGF_FE_SOFT_RESET {
12720 * DIGF_BE_SOFT_RESET enum
12723 typedef enum DIGF_BE_SOFT_RESET {
12729 * DIGG_FE_SOFT_RESET enum
12732 typedef enum DIGG_FE_SOFT_RESET {
12738 * DIGG_BE_SOFT_RESET enum
12741 typedef enum DIGG_BE_SOFT_RESET {
12747 * DPDBG_SOFT_RESET enum
12750 typedef enum DPDBG_SOFT_RESET {
12756 * DIGLPA_FE_SOFT_RESET enum
12759 typedef enum DIGLPA_FE_SOFT_RESET {
12765 * DIGLPA_BE_SOFT_RESET enum
12768 typedef enum DIGLPA_BE_SOFT_RESET {
12774 * DIGLPB_FE_SOFT_RESET enum
12777 typedef enum DIGLPB_FE_SOFT_RESET {
12783 * DIGLPB_BE_SOFT_RESET enum
12786 typedef enum DIGLPB_BE_SOFT_RESET {
12792 * GENERICA_STEREOSYNC_SEL enum
12795 typedef enum GENERICA_STEREOSYNC_SEL {
12806 * GENERICB_STEREOSYNC_SEL enum
12809 typedef enum GENERICB_STEREOSYNC_SEL {
12820 * DCO_DBG_BLOCK_SEL enum
12823 typedef enum DCO_DBG_BLOCK_SEL {
12882 * DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE enum
12885 typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE {
12891 * FMT420_MEMORY_SOURCE_SEL enum
12894 typedef enum FMT420_MEMORY_SOURCE_SEL {
12909 * DOUT_I2C_CONTROL_GO enum
12912 typedef enum DOUT_I2C_CONTROL_GO {
12918 * DOUT_I2C_CONTROL_SOFT_RESET enum
12921 typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
12927 * DOUT_I2C_CONTROL_SEND_RESET enum
12930 typedef enum DOUT_I2C_CONTROL_SEND_RESET {
12936 * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
12939 typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
12945 * DOUT_I2C_CONTROL_DDC_SELECT enum
12948 typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
12959 * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
12962 typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
12970 * DOUT_I2C_CONTROL_DBG_REF_SEL enum
12973 typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
12979 * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
12982 typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
12990 * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
12993 typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
12999 * DOUT_I2C_ARBITRATION_ABORT_XFER enum
13002 typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
13008 * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
13011 typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
13017 * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
13020 typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
13026 * DOUT_I2C_ACK enum
13029 typedef enum DOUT_I2C_ACK {
13035 * DOUT_I2C_DDC_SPEED_THRESHOLD enum
13038 typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
13046 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
13049 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
13055 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
13058 typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
13064 * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
13067 typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
13073 * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
13076 typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
13082 * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
13085 typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
13091 * DOUT_I2C_DATA_INDEX_WRITE enum
13094 typedef enum DOUT_I2C_DATA_INDEX_WRITE {
13100 * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
13103 typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
13109 * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
13112 typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
13122 * FBC_IDLE_MASK_MASK_BITS enum
13125 typedef enum FBC_IDLE_MASK_MASK_BITS {
13165 * DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum
13168 typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL {
13176 * DPCSRX_DBG_CFGCLK_SEL enum
13179 typedef enum DPCSRX_DBG_CFGCLK_SEL {
13187 * DPCSRX_RX_SYMCLK_SEL enum
13190 typedef enum DPCSRX_RX_SYMCLK_SEL {
13201 * DPCSTX_DBG_CFGCLK_SEL enum
13204 typedef enum DPCSTX_DBG_CFGCLK_SEL {
13212 * DPCSTX_TX_SYMCLK_SEL enum
13215 typedef enum DPCSTX_TX_SYMCLK_SEL {
13222 * DPCSTX_TX_SYMCLK_DIV2_SEL enum
13225 typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL {
13239 * SurfaceNumber enum
13242 typedef enum SurfaceNumber {
13254 * SurfaceSwap enum
13257 typedef enum SurfaceSwap {
13265 * CBMode enum
13268 typedef enum CBMode {
13279 * RoundMode enum
13282 typedef enum RoundMode {
13288 * SourceFormat enum
13291 typedef enum SourceFormat {
13299 * BlendOp enum
13302 typedef enum BlendOp {
13327 * CombFunc enum
13330 typedef enum CombFunc {
13339 * BlendOpt enum
13342 typedef enum BlendOpt {
13354 * CmaskCode enum
13357 typedef enum CmaskCode {
13377 * CmaskAddr enum
13380 typedef enum CmaskAddr {
13387 * MemArbMode enum
13390 typedef enum MemArbMode {
13398 * CBPerfSel enum
13401 typedef enum CBPerfSel {
13810 * CBPerfOpFilterSel enum
13813 typedef enum CBPerfOpFilterSel {
13823 * CBPerfClearFilterSel enum
13826 typedef enum CBPerfClearFilterSel {
13836 * TC_OP_MASKS enum
13839 typedef enum TC_OP_MASKS {
13846 * TC_OP enum
13849 typedef enum TC_OP {
13981 * TC_CHUB_REQ_CREDITS_ENUM enum
13984 typedef enum TC_CHUB_REQ_CREDITS_ENUM {
13989 * CHUB_TC_RET_CREDITS_ENUM enum
13992 typedef enum CHUB_TC_RET_CREDITS_ENUM {
13997 * TC_NACKS enum
14000 typedef enum TC_NACKS {
14008 * TC_EA_CID enum
14011 typedef enum TC_EA_CID {
14035 * SPI_SAMPLE_CNTL enum
14038 typedef enum SPI_SAMPLE_CNTL {
14046 * SPI_FOG_MODE enum
14049 typedef enum SPI_FOG_MODE {
14057 * SPI_PNT_SPRITE_OVERRIDE enum
14060 typedef enum SPI_PNT_SPRITE_OVERRIDE {
14069 * SPI_PERFCNT_SEL enum
14072 typedef enum SPI_PERFCNT_SEL {
14273 * SPI_SHADER_FORMAT enum
14276 typedef enum SPI_SHADER_FORMAT {
14285 * SPI_SHADER_EX_FORMAT enum
14288 typedef enum SPI_SHADER_EX_FORMAT {
14302 * CLKGATE_SM_MODE enum
14305 typedef enum CLKGATE_SM_MODE {
14314 * CLKGATE_BASE_MODE enum
14317 typedef enum CLKGATE_BASE_MODE {
14327 * SQ_TEX_CLAMP enum
14330 typedef enum SQ_TEX_CLAMP {
14342 * SQ_TEX_XY_FILTER enum
14345 typedef enum SQ_TEX_XY_FILTER {
14353 * SQ_TEX_Z_FILTER enum
14356 typedef enum SQ_TEX_Z_FILTER {
14363 * SQ_TEX_MIP_FILTER enum
14366 typedef enum SQ_TEX_MIP_FILTER {
14374 * SQ_TEX_ANISO_RATIO enum
14377 typedef enum SQ_TEX_ANISO_RATIO {
14386 * SQ_TEX_DEPTH_COMPARE enum
14389 typedef enum SQ_TEX_DEPTH_COMPARE {
14401 * SQ_TEX_BORDER_COLOR enum
14404 typedef enum SQ_TEX_BORDER_COLOR {
14412 * SQ_RSRC_BUF_TYPE enum
14415 typedef enum SQ_RSRC_BUF_TYPE {
14423 * SQ_RSRC_IMG_TYPE enum
14426 typedef enum SQ_RSRC_IMG_TYPE {
14446 * SQ_RSRC_FLAT_TYPE enum
14449 typedef enum SQ_RSRC_FLAT_TYPE {
14457 * SQ_IMG_FILTER_TYPE enum
14460 typedef enum SQ_IMG_FILTER_TYPE {
14467 * SQ_SEL_XYZW01 enum
14470 typedef enum SQ_SEL_XYZW01 {
14482 * SQ_WAVE_TYPE enum
14485 typedef enum SQ_WAVE_TYPE {
14497 * SQ_THREAD_TRACE_TOKEN_TYPE enum
14500 typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
14520 * SQ_THREAD_TRACE_MISC_TOKEN_TYPE enum
14523 typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
14535 * SQ_THREAD_TRACE_INST_TYPE enum
14538 typedef enum SQ_THREAD_TRACE_INST_TYPE {
14568 * SQ_THREAD_TRACE_REG_TYPE enum
14571 typedef enum SQ_THREAD_TRACE_REG_TYPE {
14583 * SQ_THREAD_TRACE_REG_OP enum
14586 typedef enum SQ_THREAD_TRACE_REG_OP {
14592 * SQ_THREAD_TRACE_MODE_SEL enum
14595 typedef enum SQ_THREAD_TRACE_MODE_SEL {
14601 * SQ_THREAD_TRACE_CAPTURE_MODE enum
14604 typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
14611 * SQ_THREAD_TRACE_VM_ID_MASK enum
14614 typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
14621 * SQ_THREAD_TRACE_WAVE_MASK enum
14624 typedef enum SQ_THREAD_TRACE_WAVE_MASK {
14630 * SQ_THREAD_TRACE_ISSUE enum
14633 typedef enum SQ_THREAD_TRACE_ISSUE {
14641 * SQ_THREAD_TRACE_ISSUE_MASK enum
14644 typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
14652 * SQ_PERF_SEL enum
14655 typedef enum SQ_PERF_SEL {
14956 * SQ_CAC_POWER_SEL enum
14959 typedef enum SQ_CAC_POWER_SEL {
14972 * SQ_IND_CMD_CMD enum
14975 typedef enum SQ_IND_CMD_CMD {
14987 * SQ_IND_CMD_MODE enum
14990 typedef enum SQ_IND_CMD_MODE {
14999 * SQ_EDC_INFO_SOURCE enum
15002 typedef enum SQ_EDC_INFO_SOURCE {
15013 * SQ_ROUND_MODE enum
15016 typedef enum SQ_ROUND_MODE {
15024 * SQ_INTERRUPT_WORD_ENCODING enum
15027 typedef enum SQ_INTERRUPT_WORD_ENCODING {
15034 * ENUM_SQ_EXPORT_RAT_INST enum
15037 typedef enum ENUM_SQ_EXPORT_RAT_INST {
15083 * SQ_IBUF_ST enum
15086 typedef enum SQ_IBUF_ST {
15098 * SQ_INST_STR_ST enum
15101 typedef enum SQ_INST_STR_ST {
15113 * SQ_WAVE_IB_ECC_ST enum
15116 typedef enum SQ_WAVE_IB_ECC_ST {
15124 * SH_MEM_ADDRESS_MODE enum
15127 typedef enum SH_MEM_ADDRESS_MODE {
15133 * SH_MEM_ALIGNMENT_MODE enum
15136 typedef enum SH_MEM_ALIGNMENT_MODE {
15144 * SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX enum
15147 typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
15153 * SQ_LB_CTR_SEL_VALUES enum
15156 typedef enum SQ_LB_CTR_SEL_VALUES {
15327 * CSDATA_TYPE enum
15330 typedef enum CSDATA_TYPE {
15360 * VGT_OUT_PRIM_TYPE enum
15363 typedef enum VGT_OUT_PRIM_TYPE {
15382 * VGT_DI_PRIM_TYPE enum
15385 typedef enum VGT_DI_PRIM_TYPE {
15411 * VGT_DI_SOURCE_SELECT enum
15414 typedef enum VGT_DI_SOURCE_SELECT {
15422 * VGT_DI_MAJOR_MODE_SELECT enum
15425 typedef enum VGT_DI_MAJOR_MODE_SELECT {
15431 * VGT_DI_INDEX_SIZE enum
15434 typedef enum VGT_DI_INDEX_SIZE {
15441 * VGT_EVENT_TYPE enum
15444 typedef enum VGT_EVENT_TYPE {
15512 * VGT_DMA_SWAP_MODE enum
15515 typedef enum VGT_DMA_SWAP_MODE {
15523 * VGT_INDEX_TYPE_MODE enum
15526 typedef enum VGT_INDEX_TYPE_MODE {
15533 * VGT_DMA_BUF_TYPE enum
15536 typedef enum VGT_DMA_BUF_TYPE {
15544 * VGT_OUTPATH_SELECT enum
15547 typedef enum VGT_OUTPATH_SELECT {
15557 * VGT_GRP_PRIM_TYPE enum
15560 typedef enum VGT_GRP_PRIM_TYPE {
15583 * VGT_GRP_PRIM_ORDER enum
15586 typedef enum VGT_GRP_PRIM_ORDER {
15595 * VGT_GROUP_CONV_SEL enum
15598 typedef enum VGT_GROUP_CONV_SEL {
15611 * VGT_GS_MODE_TYPE enum
15614 typedef enum VGT_GS_MODE_TYPE {
15624 * VGT_GS_CUT_MODE enum
15627 typedef enum VGT_GS_CUT_MODE {
15635 * VGT_GS_OUTPRIM_TYPE enum
15638 typedef enum VGT_GS_OUTPRIM_TYPE {
15646 * VGT_CACHE_INVALID_MODE enum
15649 typedef enum VGT_CACHE_INVALID_MODE {
15656 * VGT_TESS_TYPE enum
15659 typedef enum VGT_TESS_TYPE {
15666 * VGT_TESS_PARTITION enum
15669 typedef enum VGT_TESS_PARTITION {
15677 * VGT_TESS_TOPOLOGY enum
15680 typedef enum VGT_TESS_TOPOLOGY {
15688 * VGT_RDREQ_POLICY enum
15691 typedef enum VGT_RDREQ_POLICY {
15697 * VGT_DIST_MODE enum
15700 typedef enum VGT_DIST_MODE {
15708 * VGT_STAGES_LS_EN enum
15711 typedef enum VGT_STAGES_LS_EN {
15719 * VGT_STAGES_HS_EN enum
15722 typedef enum VGT_STAGES_HS_EN {
15728 * VGT_STAGES_ES_EN enum
15731 typedef enum VGT_STAGES_ES_EN {
15739 * VGT_STAGES_GS_EN enum
15742 typedef enum VGT_STAGES_GS_EN {
15748 * VGT_STAGES_VS_EN enum
15751 typedef enum VGT_STAGES_VS_EN {
15759 * VGT_PERFCOUNT_SELECT enum
15762 typedef enum VGT_PERFCOUNT_SELECT {
15913 * IA_PERFCOUNT_SELECT enum
15916 typedef enum IA_PERFCOUNT_SELECT {
15944 * WD_PERFCOUNT_SELECT enum
15947 typedef enum WD_PERFCOUNT_SELECT {
15988 * WD_IA_DRAW_TYPE enum
15991 typedef enum WD_IA_DRAW_TYPE {
16003 * WD_IA_DRAW_REG_XFER enum
16006 typedef enum WD_IA_DRAW_REG_XFER {
16012 * WD_IA_DRAW_SOURCE enum
16015 typedef enum WD_IA_DRAW_SOURCE {
16033 * GB_EDC_DED_MODE enum
16036 typedef enum GB_EDC_DED_MODE {
16059 * TA_TC_ADDR_MODES enum
16062 typedef enum TA_TC_ADDR_MODES {
16073 * TA_PERFCOUNT_SEL enum
16076 typedef enum TA_PERFCOUNT_SEL {
16199 * TD_PERFCOUNT_SEL enum
16202 typedef enum TD_PERFCOUNT_SEL {
16263 * TCP_PERFCOUNT_SELECT enum
16266 typedef enum TCP_PERFCOUNT_SELECT {
16466 * TCP_CACHE_POLICIES enum
16469 typedef enum TCP_CACHE_POLICIES {
16477 * TCP_CACHE_STORE_POLICIES enum
16480 typedef enum TCP_CACHE_STORE_POLICIES {
16486 * TCP_WATCH_MODES enum
16489 typedef enum TCP_WATCH_MODES {
16497 * TCP_DSM_DATA_SEL enum
16500 typedef enum TCP_DSM_DATA_SEL {
16508 * TCP_DSM_SINGLE_WRITE enum
16511 typedef enum TCP_DSM_SINGLE_WRITE {
16517 * TCP_DSM_INJECT_SEL enum
16520 typedef enum TCP_DSM_INJECT_SEL {
16532 * TCC_PERF_SEL enum
16535 typedef enum TCC_PERF_SEL {
16779 * TCA_PERF_SEL enum
16782 typedef enum TCA_PERF_SEL {
16825 * GRBM_PERF_SEL enum
16828 typedef enum GRBM_PERF_SEL {
16870 * GRBM_SE0_PERF_SEL enum
16873 typedef enum GRBM_SE0_PERF_SEL {
16893 * GRBM_SE1_PERF_SEL enum
16896 typedef enum GRBM_SE1_PERF_SEL {
16916 * GRBM_SE2_PERF_SEL enum
16919 typedef enum GRBM_SE2_PERF_SEL {
16939 * GRBM_SE3_PERF_SEL enum
16942 typedef enum GRBM_SE3_PERF_SEL {
16966 * CP_RING_ID enum
16969 typedef enum CP_RING_ID {
16977 * CP_PIPE_ID enum
16980 typedef enum CP_PIPE_ID {
16988 * CP_ME_ID enum
16991 typedef enum CP_ME_ID {
16999 * SPM_PERFMON_STATE enum
17002 typedef enum SPM_PERFMON_STATE {
17012 * CP_PERFMON_STATE enum
17015 typedef enum CP_PERFMON_STATE {
17025 * CP_PERFMON_ENABLE_MODE enum
17028 typedef enum CP_PERFMON_ENABLE_MODE {
17036 * CPG_PERFCOUNT_SEL enum
17039 typedef enum CPG_PERFCOUNT_SEL {
17092 * CPF_PERFCOUNT_SEL enum
17095 typedef enum CPF_PERFCOUNT_SEL {
17120 * CPC_PERFCOUNT_SEL enum
17123 typedef enum CPC_PERFCOUNT_SEL {
17152 * CP_ALPHA_TAG_RAM_SEL enum
17155 typedef enum CP_ALPHA_TAG_RAM_SEL {
19462 * SX_BLEND_OPT enum
19465 typedef enum SX_BLEND_OPT {
19477 * SX_OPT_COMB_FCN enum
19480 typedef enum SX_OPT_COMB_FCN {
19492 * SX_DOWNCONVERT_FORMAT enum
19495 typedef enum SX_DOWNCONVERT_FORMAT {
19510 * SX_PERFCOUNTER_VALS enum
19513 typedef enum SX_PERFCOUNTER_VALS {
19719 * ForceControl enum
19722 typedef enum ForceControl {
19730 * ZSamplePosition enum
19733 typedef enum ZSamplePosition {
19739 * ZOrder enum
19742 typedef enum ZOrder {
19750 * ZpassControl enum
19753 typedef enum ZpassControl {
19760 * ZModeForce enum
19763 typedef enum ZModeForce {
19771 * ZLimitSumm enum
19774 typedef enum ZLimitSumm {
19782 * CompareFrag enum
19785 typedef enum CompareFrag {
19797 * StencilOp enum
19800 typedef enum StencilOp {
19820 * ConservativeZExport enum
19823 typedef enum ConservativeZExport {
19831 * DbPSLControl enum
19834 typedef enum DbPSLControl {
19842 * DbPRTFaultBehavior enum
19845 typedef enum DbPRTFaultBehavior {
19853 * PerfCounter_Vals enum
19856 typedef enum PerfCounter_Vals {
20149 * RingCounterControl enum
20152 typedef enum RingCounterControl {
20159 * DbMemArbWatermarks enum
20162 typedef enum DbMemArbWatermarks {
20174 * DFSMFlushEvents enum
20177 typedef enum DFSMFlushEvents {
20187 * PixelPipeCounterId enum
20190 typedef enum PixelPipeCounterId {
20202 * PixelPipeStride enum
20205 typedef enum PixelPipeStride {
20217 * TEX_BORDER_COLOR_TYPE enum
20220 typedef enum TEX_BORDER_COLOR_TYPE {
20228 * TEX_CHROMA_KEY enum
20231 typedef enum TEX_CHROMA_KEY {
20239 * TEX_CLAMP enum
20242 typedef enum TEX_CLAMP {
20254 * TEX_COORD_TYPE enum
20257 typedef enum TEX_COORD_TYPE {
20263 * TEX_DEPTH_COMPARE_FUNCTION enum
20266 typedef enum TEX_DEPTH_COMPARE_FUNCTION {
20278 * TEX_DIM enum
20281 typedef enum TEX_DIM {
20293 * TEX_FORMAT_COMP enum
20296 typedef enum TEX_FORMAT_COMP {
20304 * TEX_MAX_ANISO_RATIO enum
20307 typedef enum TEX_MAX_ANISO_RATIO {
20319 * TEX_MIP_FILTER enum
20322 typedef enum TEX_MIP_FILTER {
20330 * TEX_REQUEST_SIZE enum
20333 typedef enum TEX_REQUEST_SIZE {
20341 * TEX_SAMPLER_TYPE enum
20344 typedef enum TEX_SAMPLER_TYPE {
20350 * TEX_XY_FILTER enum
20353 typedef enum TEX_XY_FILTER {
20361 * TEX_Z_FILTER enum
20364 typedef enum TEX_Z_FILTER {
20372 * VTX_CLAMP enum
20375 typedef enum VTX_CLAMP {
20381 * VTX_FETCH_TYPE enum
20384 typedef enum VTX_FETCH_TYPE {
20392 * VTX_FORMAT_COMP_ALL enum
20395 typedef enum VTX_FORMAT_COMP_ALL {
20401 * VTX_MEM_REQUEST_SIZE enum
20404 typedef enum VTX_MEM_REQUEST_SIZE {
20410 * TVX_DATA_FORMAT enum
20413 typedef enum TVX_DATA_FORMAT {
20481 * TVX_DST_SEL enum
20484 typedef enum TVX_DST_SEL {
20496 * TVX_ENDIAN_SWAP enum
20499 typedef enum TVX_ENDIAN_SWAP {
20507 * TVX_INST enum
20510 typedef enum TVX_INST {
20546 * TVX_NUM_FORMAT_ALL enum
20549 typedef enum TVX_NUM_FORMAT_ALL {
20557 * TVX_SRC_SEL enum
20560 typedef enum TVX_SRC_SEL {
20570 * TVX_SRF_MODE_ALL enum
20573 typedef enum TVX_SRF_MODE_ALL {
20579 * TVX_TYPE enum
20582 typedef enum TVX_TYPE {
20594 * SU_PERFCNT_SEL enum
20597 typedef enum SU_PERFCNT_SEL {
20754 * SC_PERFCNT_SEL enum
20757 typedef enum SC_PERFCNT_SEL {
21192 * SePairXsel enum
21195 typedef enum SePairXsel {
21204 * SePairYsel enum
21207 typedef enum SePairYsel {
21216 * SePairMap enum
21219 typedef enum SePairMap {
21227 * SeXsel enum
21230 typedef enum SeXsel {
21239 * SeYsel enum
21242 typedef enum SeYsel {
21251 * SeMap enum
21254 typedef enum SeMap {
21262 * ScXsel enum
21265 typedef enum ScXsel {
21273 * ScYsel enum
21276 typedef enum ScYsel {
21284 * ScMap enum
21287 typedef enum ScMap {
21295 * PkrXsel2 enum
21298 typedef enum PkrXsel2 {
21306 * PkrXsel enum
21309 typedef enum PkrXsel {
21317 * PkrYsel enum
21320 typedef enum PkrYsel {
21328 * PkrMap enum
21331 typedef enum PkrMap {
21339 * RbXsel enum
21342 typedef enum RbXsel {
21348 * RbYsel enum
21351 typedef enum RbYsel {
21357 * RbXsel2 enum
21360 typedef enum RbXsel2 {
21368 * RbMap enum
21371 typedef enum RbMap {
21379 * BinningMode enum
21382 typedef enum BinningMode {
21390 * BinEventCntl enum
21393 typedef enum BinEventCntl {
21400 * CovToShaderSel enum
21403 typedef enum CovToShaderSel {
21415 * RMIPerfSel enum
21418 typedef enum RMIPerfSel {
21658 * IH_PERF_SEL enum
21661 typedef enum IH_PERF_SEL {
22181 * SEM_PERF_SEL enum
22184 typedef enum SEM_PERF_SEL {
22366 * SDMA_PERF_SEL enum
22369 typedef enum SDMA_PERF_SEL {
22477 * ENUM_XDMA_LOCAL_SW_MODE enum
22480 typedef enum ENUM_XDMA_LOCAL_SW_MODE {
22491 * ENUM_XDMA_SLV_ALPHA_POSITION enum
22494 typedef enum ENUM_XDMA_SLV_ALPHA_POSITION {
22506 * ENUM_XDMA_MSTR_ALPHA_POSITION enum
22509 typedef enum ENUM_XDMA_MSTR_ALPHA_POSITION {
22517 * ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL enum
22520 typedef enum ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL {