Lines Matching refs:uint8_t
52 #ifndef uint8_t
53 typedef unsigned char uint8_t; typedef
228 …uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compa…
229 …uint8_t content_revision; //change it when a data table has a structure change, or a hw function…
238 …uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to d…
441 uint8_t h_border;
442 uint8_t v_border;
444 uint8_t atom_mode_id;
445 uint8_t refreshrate;
484 uint8_t mem_module_id;
485 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
486 uint8_t reserved1[2];
520 uint8_t mem_module_id;
521 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
522 uint8_t reserved1[2];
525 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
526 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
527 uint8_t board_i2c_feature_slave_addr;
528 uint8_t reserved3;
548 uint8_t mem_module_id;
549 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
550 uint8_t reserved1[2];
553 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
554 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
555 uint8_t board_i2c_feature_slave_addr;
556 uint8_t reserved3;
580 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
581 uint8_t pwr_on_de_to_vary_bl;
582 uint8_t pwr_down_vary_bloff_to_de;
583 uint8_t pwr_down_de_to_digoff;
584 uint8_t pwr_off_delay;
585 uint8_t pwr_on_vary_bl_to_blon;
586 uint8_t pwr_down_bloff_to_vary_bloff;
587 uint8_t panel_bpc;
588 uint8_t dpcd_edp_config_cap;
589 uint8_t dpcd_max_link_rate;
590 uint8_t dpcd_max_lane_count;
591 uint8_t dpcd_max_downspread;
592 uint8_t min_allowed_bl_level;
593 uint8_t max_allowed_bl_level;
594 uint8_t bootup_bl_level;
595 uint8_t dplvdsrxid;
622 uint8_t gpio_bitshift;
623 uint8_t gpio_mask_bitshift;
624 uint8_t gpio_id;
625 uint8_t reserved;
696 uint8_t record_type; //An emun to indicate the record type
697 uint8_t record_size; //The size of the whole record in byte
703 uint8_t i2c_id;
704 …uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached …
710 …uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info …
711 uint8_t plugin_pin_state;
746 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
747 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
753 uint8_t flag; // Future expnadibility
754 uint8_t number_of_pins; // Number of GPIO pins used to control the object
792 uint8_t hpd_pin_map[8];
798 uint8_t aux_ddc_map[8];
805 uint8_t maxtmdsclkrate_in2_5mhz;
806 uint8_t reserved;
812 uint8_t connector_type;
813 uint8_t position;
829 uint8_t bracketlen;
830 uint8_t bracketwidth;
831 uint8_t conn_num;
832 uint8_t reserved;
856 uint8_t priority_id;
857 uint8_t reserved;
864 uint8_t number_of_path;
865 uint8_t reserved;
888 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
889 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
890 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
891 uint8_t ss_reserved;
892 …uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable wh…
893 uint8_t reserved1[3];
896 uint8_t dceip_min_ver;
897 uint8_t dceip_max_ver;
898 uint8_t max_disp_pipe_num;
899 uint8_t max_vbios_active_disp_pipe_num;
900 uint8_t max_ppll_num;
901 uint8_t max_disp_phy_num;
902 uint8_t max_aux_pairs;
903 uint8_t remotedisplayconfig;
904 uint8_t reserved3[8];
921 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
922 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
923 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
924 uint8_t ss_reserved;
925 …uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable …
926 …uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingT…
927 …uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable …
928 …uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable …
931 uint8_t dcnip_min_ver;
932 uint8_t dcnip_max_ver;
933 uint8_t max_disp_pipe_num;
934 uint8_t max_vbios_active_disp_pipe_num;
935 uint8_t max_ppll_num;
936 uint8_t max_disp_phy_num;
937 uint8_t max_aux_pairs;
938 uint8_t remotedisplayconfig;
939 uint8_t reserved3[8];
964 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
965 uint8_t hpdlut_index; //An index into external HPD pin LUT
967 …uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapp…
968 …uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not inv…
984 …uint8_t guid[16]; // a GUID is a 16 byte long st…
986 …uint8_t checksum; // a simple Checksum of the su…
987 uint8_t stereopinid; // use for eDP panel
988 uint8_t remotedisplayconfig;
989 uint8_t edptolvdsrxid;
990 …uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate …
991 uint8_t reserved[3]; // for potential expansion
1002 uint8_t profile_id; // SENSOR_PROFILES
1013 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
1014 uint8_t module_name[8];
1020 uint8_t flashlight_id; // 0: Rear, 1: Front
1021 uint8_t name[8];
1037 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1038 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1040 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1041 …uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_e…
1042 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1043 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1047 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1049 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1050 …uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_e…
1054 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1055 uint8_t version;
1070 uint8_t sym_clk;
1071 uint8_t dig_mode;
1072 uint8_t phy_sel;
1074 uint8_t common_seldeemph60__deemph_6db_4_val;
1075 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1076 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1077 uint8_t margin_deemph_lane0__deemph_sel_val;
1081 uint8_t ucI2cRegIndex;
1082 uint8_t ucI2cRegVal;
1086 uint8_t HdmiSlvAddr;
1087 uint8_t HdmiRegNum;
1088 uint8_t Hdmi6GRegNum;
1111 …uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type …
1112 uint8_t umachannelnumber; // number of memory channels
1113 …uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1114 uint8_t pwr_on_de_to_vary_bl;
1115 uint8_t pwr_down_vary_bloff_to_de;
1116 uint8_t pwr_down_de_to_digoff;
1117 uint8_t pwr_off_delay;
1118 uint8_t pwr_on_vary_bl_to_blon;
1119 uint8_t pwr_down_bloff_to_vary_bloff;
1120 uint8_t min_allowed_bl_level;
1121 uint8_t htc_hyst_limit;
1122 uint8_t htc_tmp_limit;
1123 uint8_t reserved1;
1124 uint8_t reserved2;
1221 uint8_t gfxip_min_ver;
1222 uint8_t gfxip_max_ver;
1223 uint8_t max_shader_engines;
1224 uint8_t max_tile_pipes;
1225 uint8_t max_cu_per_sh;
1226 uint8_t max_sh_per_se;
1227 uint8_t max_backends_per_se;
1228 uint8_t max_texture_channel_caches;
1241 uint8_t gfxip_min_ver;
1242 uint8_t gfxip_max_ver;
1243 uint8_t max_shader_engines;
1244 uint8_t max_tile_pipes;
1245 uint8_t max_cu_per_sh;
1246 uint8_t max_sh_per_se;
1247 uint8_t max_backends_per_se;
1248 uint8_t max_texture_channel_caches;
1257 uint8_t active_cu_per_sh;
1258 uint8_t active_rb_per_se;
1266 uint8_t gfxip_min_ver;
1267 uint8_t gfxip_max_ver;
1268 uint8_t max_shader_engines;
1269 uint8_t reserved;
1270 uint8_t max_cu_per_sh;
1271 uint8_t max_sh_per_se;
1272 uint8_t max_backends_per_se;
1273 uint8_t max_texture_channel_caches;
1282 uint8_t active_cu_per_sh;
1283 uint8_t active_rb_per_se;
1291 uint8_t gc_num_max_gs_thds;
1292 uint8_t gc_gs_table_depth;
1293 uint8_t gc_double_offchip_lds_buffer;
1294 uint8_t gc_max_scratch_slots_per_cu;
1307 uint8_t smuip_min_ver;
1308 uint8_t smuip_max_ver;
1309 uint8_t smu_rsd1;
1310 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1316 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1317 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1318 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1319 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1320 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1321 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1322 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1323 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1328 uint8_t smuip_min_ver;
1329 uint8_t smuip_max_ver;
1330 uint8_t smu_rsd1;
1331 uint8_t gpuclk_ss_mode;
1337 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1338 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1339 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1340 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1341 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1342 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1343 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1344 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1345 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
1346 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1361 uint8_t smuip_min_ver;
1362 uint8_t smuip_max_ver;
1363 uint8_t waflclk_ss_mode;
1364 uint8_t gpuclk_ss_mode;
1370 …uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switchi…
1371 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1372 …uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event…
1373 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1374 …uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event …
1375 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1376 …uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff mea…
1377 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1378 …uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff mea…
1379 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1407 uint8_t liquid1_i2c_address;
1408 uint8_t liquid2_i2c_address;
1409 uint8_t vr_i2c_address;
1410 uint8_t plx_i2c_address;
1412 uint8_t liquid_i2c_linescl;
1413 uint8_t liquid_i2c_linesda;
1414 uint8_t vr_i2c_linescl;
1415 uint8_t vr_i2c_linesda;
1417 uint8_t plx_i2c_linescl;
1418 uint8_t plx_i2c_linesda;
1419 uint8_t vrsensorpresent;
1420 uint8_t liquidsensorpresent;
1425 uint8_t vddgfxvrmapping;
1426 uint8_t vddsocvrmapping;
1427 uint8_t vddmem0vrmapping;
1428 uint8_t vddmem1vrmapping;
1430 uint8_t gfxulvphasesheddingmask;
1431 uint8_t soculvphasesheddingmask;
1432 uint8_t padding8_v[2];
1435 uint8_t gfxoffset;
1436 uint8_t padding_telemetrygfx;
1439 uint8_t socoffset;
1440 uint8_t padding_telemetrysoc;
1443 uint8_t mem0offset;
1444 uint8_t padding_telemetrymem0;
1447 uint8_t mem1offset;
1448 uint8_t padding_telemetrymem1;
1450 uint8_t acdcgpio;
1451 uint8_t acdcpolarity;
1452 uint8_t vr0hotgpio;
1453 uint8_t vr0hotpolarity;
1455 uint8_t vr1hotgpio;
1456 uint8_t vr1hotpolarity;
1457 uint8_t padding1;
1458 uint8_t padding2;
1460 uint8_t ledpin0;
1461 uint8_t ledpin1;
1462 uint8_t ledpin2;
1463 uint8_t padding8_4;
1465 uint8_t pllgfxclkspreadenabled;
1466 uint8_t pllgfxclkspreadpercent;
1469 uint8_t uclkspreadenabled;
1470 uint8_t uclkspreadpercent;
1473 uint8_t socclkspreadenabled;
1474 uint8_t socclkspreadpercent;
1477 uint8_t acggfxclkspreadenabled;
1478 uint8_t acggfxclkspreadpercent;
1481 uint8_t Vr2_I2C_address;
1482 uint8_t padding_vr2[3];
1495 uint8_t liquid1_i2c_address;
1496 uint8_t liquid2_i2c_address;
1497 uint8_t vr_i2c_address;
1498 uint8_t plx_i2c_address;
1500 uint8_t liquid_i2c_linescl;
1501 uint8_t liquid_i2c_linesda;
1502 uint8_t vr_i2c_linescl;
1503 uint8_t vr_i2c_linesda;
1505 uint8_t plx_i2c_linescl;
1506 uint8_t plx_i2c_linesda;
1507 uint8_t vrsensorpresent;
1508 uint8_t liquidsensorpresent;
1513 uint8_t vddgfxvrmapping;
1514 uint8_t vddsocvrmapping;
1515 uint8_t vddmem0vrmapping;
1516 uint8_t vddmem1vrmapping;
1518 uint8_t gfxulvphasesheddingmask;
1519 uint8_t soculvphasesheddingmask;
1520 uint8_t externalsensorpresent;
1521 uint8_t padding8_v;
1524 uint8_t gfxoffset;
1525 uint8_t padding_telemetrygfx;
1528 uint8_t socoffset;
1529 uint8_t padding_telemetrysoc;
1532 uint8_t mem0offset;
1533 uint8_t padding_telemetrymem0;
1536 uint8_t mem1offset;
1537 uint8_t padding_telemetrymem1;
1539 uint8_t acdcgpio;
1540 uint8_t acdcpolarity;
1541 uint8_t vr0hotgpio;
1542 uint8_t vr0hotpolarity;
1544 uint8_t vr1hotgpio;
1545 uint8_t vr1hotpolarity;
1546 uint8_t padding1;
1547 uint8_t padding2;
1549 uint8_t ledpin0;
1550 uint8_t ledpin1;
1551 uint8_t ledpin2;
1552 uint8_t padding8_4;
1554 uint8_t pllgfxclkspreadenabled;
1555 uint8_t pllgfxclkspreadpercent;
1558 uint8_t uclkspreadenabled;
1559 uint8_t uclkspreadpercent;
1562 uint8_t fclkspreadenabled;
1563 uint8_t fclkspreadpercent;
1566 uint8_t fllgfxclkspreadenabled;
1567 uint8_t fllgfxclkspreadpercent;
1591 uint8_t vddgfxvrmapping;
1592 uint8_t vddsocvrmapping;
1593 uint8_t vddmem0vrmapping;
1594 uint8_t vddmem1vrmapping;
1596 uint8_t gfxulvphasesheddingmask;
1597 uint8_t soculvphasesheddingmask;
1598 uint8_t externalsensorpresent;
1599 uint8_t padding8_v;
1602 uint8_t gfxoffset;
1603 uint8_t padding_telemetrygfx;
1606 uint8_t socoffset;
1607 uint8_t padding_telemetrysoc;
1610 uint8_t mem0offset;
1611 uint8_t padding_telemetrymem0;
1614 uint8_t mem1offset;
1615 uint8_t padding_telemetrymem1;
1618 uint8_t acdcgpio;
1619 uint8_t acdcpolarity;
1620 uint8_t vr0hotgpio;
1621 uint8_t vr0hotpolarity;
1623 uint8_t vr1hotgpio;
1624 uint8_t vr1hotpolarity;
1625 uint8_t padding1;
1626 uint8_t padding2;
1629 uint8_t ledpin0;
1630 uint8_t ledpin1;
1631 uint8_t ledpin2;
1632 uint8_t padding8_4;
1635 uint8_t pllgfxclkspreadenabled;
1636 uint8_t pllgfxclkspreadpercent;
1640 uint8_t uclkspreadenabled;
1641 uint8_t uclkspreadpercent;
1645 uint8_t fclkspreadenabled;
1646 uint8_t fclkspreadpercent;
1650 uint8_t fllgfxclkspreadenabled;
1651 uint8_t fllgfxclkspreadpercent;
1697 uint8_t Enabled;
1698 uint8_t Speed;
1699 uint8_t Padding[2];
1701 uint8_t ControllerPort;
1702 uint8_t ControllerName;
1703 uint8_t ThermalThrotter;
1704 uint8_t I2cProtocol;
1718 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
1719 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
1720 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
1721 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
1723 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1724 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
1725 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
1726 uint8_t Padding8_V;
1730 uint8_t GfxOffset; // in Amps
1731 uint8_t Padding_TelemetryGfx;
1733 uint8_t SocOffset; // in Amps
1734 uint8_t Padding_TelemetrySoc;
1737 uint8_t Mem0Offset; // in Amps
1738 uint8_t Padding_TelemetryMem0;
1741 uint8_t Mem1Offset; // in Amps
1742 uint8_t Padding_TelemetryMem1;
1745 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
1746 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
1747 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
1748 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
1750 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
1751 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
1752 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
1753 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
1756 uint8_t LedPin0; // GPIO number for LedPin[0]
1757 uint8_t LedPin1; // GPIO number for LedPin[1]
1758 uint8_t LedPin2; // GPIO number for LedPin[2]
1759 uint8_t padding8_4;
1762 uint8_t PllGfxclkSpreadEnabled; // on or off
1763 uint8_t PllGfxclkSpreadPercent; // Q4.4
1767 uint8_t DfllGfxclkSpreadEnabled; // on or off
1768 uint8_t DfllGfxclkSpreadPercent; // Q4.4
1772 uint8_t UclkSpreadEnabled; // on or off
1773 uint8_t UclkSpreadPercent; // Q4.4
1777 uint8_t SoclkSpreadEnabled; // on or off
1778 uint8_t SocclkSpreadPercent; // Q4.4
1801 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields
1802 uint8_t vddsocvrmapping; // use vr_mapping* bitfields
1803 uint8_t vddmemvrmapping; // use vr_mapping* bitfields
1804 uint8_t boardvrmapping; // use vr_mapping* bitfields
1806 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
1807 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in)
1808 uint8_t padding8_v[2];
1812 uint8_t gfxoffset; // in amps
1813 uint8_t padding_telemetrygfx;
1816 uint8_t socoffset; // in amps
1817 uint8_t padding_telemetrysoc;
1820 uint8_t memoffset; // in amps
1821 uint8_t padding_telemetrymem;
1824 uint8_t boardoffset; // in amps
1825 uint8_t padding_telemetryboardinput;
1828 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event
1829 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event
1830 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event
1831 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event
1834 uint8_t pllgfxclkspreadenabled; // on or off
1835 uint8_t pllgfxclkspreadpercent; // q4.4
1839 uint8_t uclkspreadenabled; // on or off
1840 uint8_t uclkspreadpercent; // q4.4
1844 uint8_t fclkspreadenabled; // on or off
1845 uint8_t fclkspreadpercent; // q4.4
1850 uint8_t fllgfxclkspreadenabled; // on or off
1851 uint8_t fllgfxclkspreadpercent; // q4.4
1860 uint8_t drambitwidth; // for dram use only. see dram bit width type defines
1861 uint8_t paddingmem[3];
1868 uint8_t xgmilinkspeed[4];
1869 uint8_t xgmilinkwidth[4];
1907 uint8_t enable_gb_vdroop_table_cksoff;
1908 uint8_t enable_gb_vdroop_table_ckson;
1909 uint8_t enable_gb_fuse_table_cksoff;
1910 uint8_t enable_gb_fuse_table_ckson;
1912 uint8_t enable_apply_avfs_cksoff_voltage;
1913 uint8_t reserved;
1951 uint8_t enable_gb_vdroop_table_cksoff;
1952 uint8_t enable_gb_vdroop_table_ckson;
1953 uint8_t enable_gb_fuse_table_cksoff;
1954 uint8_t enable_gb_fuse_table_ckson;
1956 uint8_t enable_apply_avfs_cksoff_voltage;
1957 uint8_t reserved;
1976 uint8_t enable_acg_gb_vdroop_table;
1977 uint8_t enable_acg_gb_fuse_table;
2000 uint8_t uvdip_min_ver;
2001 uint8_t uvdip_max_ver;
2002 uint8_t vceip_min_ver;
2003 uint8_t vceip_max_ver;
2028 uint8_t umcip_min_ver;
2029 uint8_t umcip_max_ver;
2030 uint8_t vram_type; //enum of atom_dgpu_vram_type
2031 uint8_t umc_config;
2055 uint8_t umcip_min_ver;
2056 uint8_t umcip_max_ver;
2057 uint8_t vram_type; //enum of atom_dgpu_vram_type
2058 uint8_t umc_config;
2075 uint8_t umcip_min_ver;
2076 uint8_t umcip_max_ver;
2077 uint8_t vram_type; //enum of atom_dgpu_vram_type
2078 uint8_t umc_config;
2099 uint8_t ext_memory_id; // Current memory module ID
2100 uint8_t memory_type; // enum of atom_dgpu_vram_type
2101 uint8_t channel_num; // Number of mem. channels supported in this module
2102 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2103 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2104 uint8_t tunningset_id; // MC phy registers set per.
2105 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2106 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2107 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id
2108 uint8_t vram_rsd2; // reserved
2122 uint8_t vram_module_num; // indicate number of VRAM module
2123 uint8_t umcip_min_ver;
2124 uint8_t umcip_max_ver;
2125 …uint8_t mc_phy_tile_num; // indicate the MCD tile number which use i…
2177 uint8_t ext_memory_id; // Current memory module ID
2178 uint8_t memory_type; // enum of atom_dgpu_vram_type
2179 uint8_t channel_num; // Number of mem. channels supported in this module
2180 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
2181 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
2182 uint8_t tunningset_id; // MC phy registers set per
2183 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
2184 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
2185 uint8_t vram_flags; // bit0= bankgroup enable
2186 uint8_t vram_rsd2; // reserved
2204 uint8_t vram_module_num; // indicate number of VRAM module
2205 uint8_t umcip_min_ver;
2206 uint8_t umcip_max_ver;
2207 …uint8_t mc_phy_tile_num; // indicate the MCD tile number which use i…
2223 uint8_t voltage_type; //enum atom_voltage_type
2224 uint8_t voltage_mode; //enum atom_voltage_object_mode
2242 uint8_t regulator_id; //Indicate Voltage Regulator Id
2243 uint8_t i2c_id;
2244 uint8_t i2c_slave_addr;
2245 uint8_t i2c_control_offset;
2246 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
2247 …uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in un…
2248 uint8_t reserved[2];
2269 …uint8_t gpio_control_id; // default is 0 which indicate control through CG VI…
2270 …uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value L…
2271 uint8_t phase_delay_us; // phase delay in unit of micro second
2272 uint8_t reserved;
2280 …uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and…
2281 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
2282 uint8_t psi0_enable; //
2283 uint8_t maxvstep;
2284 uint8_t telemetry_offset;
2285 uint8_t telemetry_gain;
2292 uint8_t merged_powerrail_type; //enum atom_voltage_type
2293 uint8_t reserved[3];
2438 uint8_t voltagetype; /* enum atom_voltage_type */
2439 …uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_…
2487 uint8_t pll_ss_enable;
2488 uint8_t reserved;
2503 uint8_t reserved;
2504 uint8_t bitslen;
2522 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
2523 …uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLO…
2524 uint8_t command; // enum of atom_get_smu_clock_info_command
2525 …uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid wh…
2662 uint8_t ucode_func_id;
2663 uint8_t ucode_reserved[3];
2678 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
2679 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
2681 uint8_t encoder_mode; // Encoder mode:
2682 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
2683 uint8_t crtc_id; // enum of atom_crtc_def
2684 …uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepc…
2685 uint8_t reserved1[2];
2724 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
2725 …uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK …
2726 …uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when u…
2727 …uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use on…
2771 uint8_t crtc_id; // enum atom_crtc_def
2772 uint8_t blanking; // enum atom_blank_crtc_command
2788 uint8_t crtc_id; // enum atom_crtc_def
2789 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2790 uint8_t padding[2];
2799 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
2800 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2801 uint8_t padding[2];
2824 uint8_t h_border;
2825 uint8_t v_border;
2826 uint8_t crtc_id; // enum atom_crtc_def
2827 uint8_t encoder_mode; // atom_encode_mode_def
2828 uint8_t padding[2];
2837 uint8_t i2cspeed_khz;
2839 uint8_t regindex;
2840 uint8_t status; /* enum atom_process_i2c_flag */
2843 uint8_t flag; /* enum atom_process_i2c_status */
2844 uint8_t trans_bytes;
2845 uint8_t slave_addr;
2846 uint8_t i2c_id;
2874 uint8_t channelid;
2876 uint8_t reply_status;
2877 uint8_t aux_delay;
2879 uint8_t dataout_len;
2880 …uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, …
2890 uint8_t crtc_id; // enum atom_crtc_def
2891 uint8_t encoder_id; // enum atom_dig_def
2892 uint8_t encode_mode; // enum atom_encode_mode_def
2893 uint8_t dst_bpc; // enum atom_panel_bit_per_color
2943 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2944 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
2945 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2946 uint8_t lanenum; // Lane number
2948 uint8_t bitpercolor;
2949 …uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz…
2950 uint8_t reserved[2];
2955 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2956 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
2957 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2958 uint8_t lanenum; // Lane number
2959 uint8_t symclk_10khz; // Symbol Clock in 10Khz
2960 uint8_t hpd_sel;
2961 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2962 uint8_t reserved[2];
2967 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2968 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
2969 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
2970 uint8_t reserved1;
2976 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2977 uint8_t action; // = rest of generic encoder command which does not carry any parameters
2978 uint8_t reserved1[2];
2997 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
2998 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
3000 uint8_t digmode; // enum atom_encode_mode_def
3001 …uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "D…
3003 uint8_t lanenum; // Lane number 1, 2, 4, 8
3005 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
3006 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
3007 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
3008 uint8_t reserved;
3086 …uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENAB…
3087 uint8_t action; //
3088 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
3089 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
3090 …uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPU…
3091 uint8_t hpd_id;
3139 uint8_t revision;
3140 uint8_t checksum;
3141 uint8_t oemId[6];
3142 uint8_t oemTableId[8]; //UINT64 OemTableId;
3150 uint8_t tableUUID[16]; //0x24
3171 uint8_t vbioscontent[1];
3176 uint8_t lib1content[1];