Lines Matching refs:ULONG
44 #ifndef ULONG
45 typedef unsigned long ULONG; typedef
262 ULONG ulPSPDirTableOffset;
427 …ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYT…
428 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
429 ULONG ulClockFreq:24;
431 ULONG ulClockFreq:24;
432 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
433 …ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYT…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
449 ULONG ulClock; //When return, [23:0] return real clock
478 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
479 ULONG ulClockFreq:24; // in unit of 10kHz
481 ULONG ulClockFreq:24; // in unit of 10kHz
482 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
497 ULONG ulClockParams; //ULONG access for BE
517 …ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register d…
518 ULONG ulClock:24; //Input= target clock, output = actual clock
520 ULONG ulClock:24; //Input= target clock, output = actual clock
521 …ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register d…
530 ULONG ulClockParams; //ULONG access for BE
547 ULONG ulReserved[2];
572 ULONG ulReserved[5];
605 ULONG ulClock;
632 ULONG ulReserved;
647 ULONG ulReserved[2];
655 ULONG ulMemoryClock;
656 ULONG ulReserved;
666 ULONG ulReserved;
687 ULONG ulTargetEngineClock; //In 10Khz unit
692 ULONG ulTargetEngineClock; //In 10Khz unit
698 ULONG ulTargetEngineClock; //In 10Khz unit
708 ULONG ulTargetMemoryClock; //In 10Khz unit
713 ULONG ulTargetMemoryClock; //In 10Khz unit
722 ULONG ulDefaultEngineClock; //In 10Khz unit
723 ULONG ulDefaultMemoryClock; //In 10Khz unit
734 ULONG ulClkFreqIn10Khz:24;
735 ULONG ucClkFlag:8;
747 ULONG ulReserved[8];
775 ULONG ulReserved[4];
804 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
1087 ULONG ulPixelClock; // Pixel Clock in 10Khz
1099 ULONG ulSymClock; // Symbol Clock in 10Khz
1113 ULONG ulReserved[2];
1121 ULONG ulReserved[2];
1569 ULONG ulSymClock; // Symbol Clock in 10Khz
1574 ULONG ulReserved;
1647 ULONG ulReserved[2];
1933 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
1948 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1950 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1953 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
1955 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1964 ULONG ulDispEngClkFreq; // dispclk frequency
1981 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
2017 …ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 1…
2032 ULONG ulReserved;
2054 …ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequ…
2065 ULONG ulReserved[2];
2076 …ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, retur…
2106 ULONG ulReserved[2];
2155 …ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pix…
2186 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
2195 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
2376 ULONG ulTargetMemoryClock; //In 10Khz unit
2673 ULONG ulReserved;
2679 ULONG ulVotlageGpioState;
2680 ULONG ulVoltageGPioMask;
2688 ULONG ulReseved;
2712 …ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, …
2734 …ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, …
2735 ULONG ulReserved[3];
2741 ULONG ulVoltageLevel; // real voltage level in unit of 0.01mv
2742 ULONG ulReserved[4];
2751 ULONG ulDfsPllOutputFreq:24;
2752 ULONG ucDfsDivider:8;
2757 ULONG ulDfsOutputFreq;
2842 ULONG ulSignature; // HW info table signature string "$ATI"
2856 ULONG ulSignature; // MM info table signature sting "$MMT"
2951 ULONG ulFirmwareRevision;
2952 ULONG ulDefaultEngineClock; //In 10Khz unit
2953 ULONG ulDefaultMemoryClock; //In 10Khz unit
2954 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2955 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2956 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2957 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2958 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2959 ULONG ulASICMaxEngineClock; //In 10Khz unit
2960 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2963 ULONG aulReservedForBIOS[3]; //Don't use them
2985 ULONG ulFirmwareRevision;
2986 ULONG ulDefaultEngineClock; //In 10Khz unit
2987 ULONG ulDefaultMemoryClock; //In 10Khz unit
2988 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2989 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2990 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2991 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2992 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2993 ULONG ulASICMaxEngineClock; //In 10Khz unit
2994 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2998 ULONG aulReservedForBIOS[2]; //Don't use them
2999 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3021 ULONG ulFirmwareRevision;
3022 ULONG ulDefaultEngineClock; //In 10Khz unit
3023 ULONG ulDefaultMemoryClock; //In 10Khz unit
3024 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3025 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3026 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3027 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3028 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3029 ULONG ulASICMaxEngineClock; //In 10Khz unit
3030 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3034 ULONG aulReservedForBIOS; //Don't use them
3035 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3036 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3058 ULONG ulFirmwareRevision;
3059 ULONG ulDefaultEngineClock; //In 10Khz unit
3060 ULONG ulDefaultMemoryClock; //In 10Khz unit
3061 ULONG ulDriverTargetEngineClock; //In 10Khz unit
3062 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
3063 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3064 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3065 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3066 ULONG ulASICMaxEngineClock; //In 10Khz unit
3067 ULONG ulASICMaxMemoryClock; //In 10Khz unit
3073 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
3074 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3097 ULONG ulFirmwareRevision;
3098 ULONG ulDefaultEngineClock; //In 10Khz unit
3099 ULONG ulDefaultMemoryClock; //In 10Khz unit
3100 ULONG ulReserved1;
3101 ULONG ulReserved2;
3102 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
3103 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
3104 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3105 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock
3106 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
3112 ULONG ulReserved4; //Was ulAsicMaximumVoltage
3113 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3147 ULONG ulFirmwareRevision;
3148 ULONG ulDefaultEngineClock; //In 10Khz unit
3149 ULONG ulDefaultMemoryClock; //In 10Khz unit
3150 ULONG ulSPLL_OutputFreq; //In 10Khz unit
3151 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
3152 …ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In…
3153 …ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In…
3154 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
3155 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ?
3156 …ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency…
3162 ULONG ulReserved4; //Was ulAsicMaximumVoltage
3163 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
3166 …ULONG ulReserved6; //Was usMinEngineClockPLL_Output and u…
3167 …ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and us…
3182 …ULONG ulReserved10[3]; // New added comparing to previous ver…
3203 ULONG ulBootUpEngineClock; //in 10kHz unit
3204 ULONG ulBootUpMemoryClock; //in 10kHz unit
3205 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
3206 ULONG ulMinSystemMemoryClock; //in 10kHz unit
3212 ULONG ulReserved[2];
3275 ULONG ulBootUpEngineClock; //in 10kHz unit
3276 ULONG ulReserved1[2]; //must be 0x0 for the reserved
3277 ULONG ulBootUpUMAClock; //in 10kHz unit
3278 ULONG ulBootUpSidePortClock; //in 10kHz unit
3279 ULONG ulMinSidePortClock; //in 10kHz unit
3280 ULONG ulReserved2[6]; //must be 0x0 for the reserved
3281 ULONG ulSystemConfig; //see explanation below
3282 ULONG ulBootUpReqDisplayVector;
3283 ULONG ulOtherDisplayMisc;
3284 ULONG ulDDISlot1Config;
3285 ULONG ulDDISlot2Config;
3290 ULONG ulDockingPinCFGInfo;
3291 ULONG ulCPUCapInfo;
3296 ULONG ulHTLinkFreq; //in 10Khz
3303 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
3304 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
3311 ULONG ulReserved3[96]; //must be 0x0
3449 ULONG ulBootUpEngineClock; //in 10kHz unit
3450 …ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the sourc…
3451 …ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relation…
3452 ULONG ulBootUpUMAClock; //in 10kHz unit
3453 ULONG ulReserved1[8]; //must be 0x0 for the reserved
3454 ULONG ulBootUpReqDisplayVector;
3455 ULONG ulOtherDisplayMisc;
3456 ULONG ulReserved2[4]; //must be 0x0 for the reserved
3457 ULONG ulSystemConfig; //TBD
3458 ULONG ulCPUCapInfo; //TBD
3464 ULONG ulReserved3[4]; //must be 0x0 for the reserved
3465 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition
3466 ULONG ulDDISlot2Config;
3467 ULONG ulDDISlot3Config;
3468 ULONG ulDDISlot4Config;
3469 ULONG ulReserved4[4]; //must be 0x0 for the reserved
3473 ULONG ulReserved5[4]; //must be 0x0 for the reserved
3474 …ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter f…
3475 …ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for …
3476 …ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for …
3477 ULONG ulReserved6[61]; //must be 0x0
3488 ULONG ulMCUcodeRomStartAddr;
3489 ULONG ulMCUcodeLength;
3490 ULONG ulSMCUcodeRomStartAddr;
3491 ULONG ulSMCUcodeLength;
3492 ULONG ulRLCVUcodeRomStartAddr;
3493 ULONG ulRLCVUcodeLength;
3494 ULONG ulTOCUcodeStartAddr;
3495 ULONG ulTOCUcodeLength;
3496 ULONG ulSMCPatchTableStartAddr;
3497 ULONG ulSmcPatchTableLength;
3498 ULONG ulSystemFlag;
3998 ULONG ulReserved0;
4036 ULONG ulReserved[2];
4333 ULONG ulStartAddrUsedByFirmware;
4347 ULONG ulStartAddrUsedByFirmware;
4726 ULONG ulACPIDeviceEnum; //Reserved for now
4826 ULONG ulStrengthControl; // DVOA strength control for CF
5128 …ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register
5163 ULONG ulGpioMaskVal; // GPIO Mask value
5173 ULONG ulMaxVoltageLevel;
5190 ULONG ulReserved;
5205 ULONG ulDPMSclk; // DPM state SCLK
5278 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5279 ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2
5288 …ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative n…
5289 ULONG ulEfuseMin; // Min
5296 ULONG ulEvvDerateTdp;
5297 ULONG ulEvvDerateTdc;
5298 ULONG ulBoardCoreTemp;
5299 ULONG ulMaxVddc;
5300 ULONG ulMinVddc;
5301 ULONG ulLoadLineSlop;
5302 ULONG ulLeakageTemp;
5303 ULONG ulLeakageVoltage;
5312 ULONG ulLkgEncodeLn_MaxDivMin;
5313 ULONG ulLkgEncodeMax;
5314 ULONG ulLkgEncodeMin;
5315 ULONG ulEfuseLogisticAlpha;
5338 ULONG ulEvvLkgFactor;
5339 ULONG ulBoardCoreTemp;
5340 ULONG ulMaxVddc;
5341 ULONG ulMinVddc;
5342 ULONG ulLoadLineSlop;
5343 ULONG ulLeakageTemp;
5344 ULONG ulLeakageVoltage;
5353 ULONG ulLkgEncodeLn_MaxDivMin;
5354 ULONG ulLkgEncodeMax;
5355 ULONG ulLkgEncodeMin;
5356 ULONG ulEfuseLogisticAlpha;
5365 ULONG ulTdpDerateDPM0;
5366 ULONG ulTdpDerateDPM1;
5367 ULONG ulTdpDerateDPM2;
5368 ULONG ulTdpDerateDPM3;
5369 ULONG ulTdpDerateDPM4;
5370 ULONG ulTdpDerateDPM5;
5371 ULONG ulTdpDerateDPM6;
5372 ULONG ulTdpDerateDPM7;
5380 ULONG ulEvvLkgFactor;
5381 ULONG ulBoardCoreTemp;
5382 ULONG ulMaxVddc;
5383 ULONG ulMinVddc;
5384 ULONG ulLoadLineSlop;
5385 ULONG ulLeakageTemp;
5386 ULONG ulLeakageVoltage;
5395 ULONG ulLkgEncodeLn_MaxDivMin;
5396 ULONG ulLkgEncodeMax;
5397 ULONG ulLkgEncodeMin;
5398 ULONG ulEfuseLogisticAlpha;
5411 ULONG ulTdpDerateDPM0;
5412 ULONG ulTdpDerateDPM1;
5413 ULONG ulTdpDerateDPM2;
5414 ULONG ulTdpDerateDPM3;
5415 ULONG ulTdpDerateDPM4;
5416 ULONG ulTdpDerateDPM5;
5417 ULONG ulTdpDerateDPM6;
5418 ULONG ulTdpDerateDPM7;
5420 ULONG ulRoAlpha;
5421 ULONG ulRoBeta;
5422 ULONG ulRoGamma;
5423 ULONG ulRoEpsilon;
5424 ULONG ulATermRo;
5425 ULONG ulBTermRo;
5426 ULONG ulCTermRo;
5427 ULONG ulSclkMargin;
5428 ULONG ulFmaxPercent;
5429 ULONG ulCRPercent;
5430 ULONG ulSFmaxPercent;
5431 ULONG ulSCRPercent;
5432 ULONG ulSDCMargine;
5439 ULONG ulEvvLkgFactor;
5440 ULONG ulBoardCoreTemp;
5441 ULONG ulMaxVddc;
5442 ULONG ulMinVddc;
5443 ULONG ulLoadLineSlop;
5444 ULONG ulLeakageTemp;
5445 ULONG ulLeakageVoltage;
5454 ULONG ulLkgEncodeLn_MaxDivMin;
5455 ULONG ulLkgEncodeMax;
5456 ULONG ulLkgEncodeMin;
5457 ULONG ulEfuseLogisticAlpha;
5466 ULONG ulTdpDerateDPM0;
5467 ULONG ulTdpDerateDPM1;
5468 ULONG ulTdpDerateDPM2;
5469 ULONG ulTdpDerateDPM3;
5470 ULONG ulTdpDerateDPM4;
5471 ULONG ulTdpDerateDPM5;
5472 ULONG ulTdpDerateDPM6;
5473 ULONG ulTdpDerateDPM7;
5475 ULONG ulEvvDefaultVddc;
5476 ULONG ulEvvNoCalcVddc;
5479 ULONG ulSM_A0;
5480 ULONG ulSM_A1;
5481 ULONG ulSM_A2;
5482 ULONG ulSM_A3;
5483 ULONG ulSM_A4;
5484 ULONG ulSM_A5;
5485 ULONG ulSM_A6;
5486 ULONG ulSM_A7;
5495 ULONG ulMargin_RO_a;
5496 ULONG ulMargin_RO_b;
5497 ULONG ulMargin_RO_c;
5498 ULONG ulMargin_fixed;
5499 ULONG ulMargin_Fmax_mean;
5500 ULONG ulMargin_plat_mean;
5501 ULONG ulMargin_Fmax_sigma;
5502 ULONG ulMargin_plat_sigma;
5503 ULONG ulMargin_DC_sigma;
5504 ULONG ulReserved[8]; // Reserved for future ASIC
5511 ULONG ulMaxVddc; //Maximum voltage for all parts, in unit of 0.01mv
5512 ULONG ulMinVddc; //Minimum voltage for all parts, in unit of 0.01mv
5516 …ULONG ulLkgEncodeLn_MaxDivMin; //value of ln(Max_Lkg_Ft/Min_Lkg_Ft ) in unit of 0.00001 ( unit=10…
5517 …ULONG ulLkgEncodeMax; //Maximum Lkg_Ft measured value ( or efuse decode value ), in unit…
5518 …ULONG ulLkgEncodeMin; //Minimum Lkg_Ft measured value ( or efuse decode value ), in unit…
5520 …ULONG ulEvvDefaultVddc; //def="EVV_DEFAULT_VDDC" descr="return default VDDC(v) when Efuse …
5521 …ULONG ulEvvNoCalcVddc; //def="EVV_NOCALC_VDDC" descr="return VDDC(v) when Calculation is …
5522 …ULONG ulSpeed_Model; //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate m…
5523 …ULONG ulSM_A0; //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="…
5524 …ULONG ulSM_A1; //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." u…
5525 …ULONG ulSM_A2; //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Mu…
5526 …ULONG ulSM_A3; //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivar…
5527 …ULONG ulSM_A4; //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." un…
5528 …ULONG ulSM_A5; //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="1…
5529 …ULONG ulSM_A6; //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multiva…
5530 …ULONG ulSM_A7; //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multiva…
5539 …ULONG ulMargin_RO_a; //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in …
5540 …ULONG ulMargin_RO_b; //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in …
5541 …ULONG ulMargin_RO_c; //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in …
5542 …ULONG ulMargin_fixed; //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, u…
5543 …ULONG ulMargin_Fmax_mean; //def="EVV_MARGIN_FMAX_MEAN" descr="Percentage to add for Fmas mea…
5544 …ULONG ulMargin_plat_mean; //def="EVV_MARGIN_PLAT_MEAN" descr="Percentage to add for platform…
5545 …ULONG ulMargin_Fmax_sigma; //def="EVV_MARGIN_FMAX_SIGMA" descr="Percentage to add for Fmax si…
5546 …ULONG ulMargin_plat_sigma; //def="EVV_MARGIN_PLAT_SIGMA" descr="Percentage to add for platfor…
5547 …ULONG ulMargin_DC_sigma; //def="EVV_MARGIN_DC_SIGMA" descr="Regulator DC tolerance margin (…
5548 ULONG ulReserved[12];
5555 ULONG ulMaxVddc;
5556 ULONG ulMinVddc;
5560 ULONG ulLkgEncodeLn_MaxDivMin;
5561 ULONG ulLkgEncodeMax;
5562 ULONG ulLkgEncodeMin;
5564 ULONG ulEvvDefaultVddc;
5565 ULONG ulEvvNoCalcVddc;
5566 ULONG ulSpeed_Model;
5567 ULONG ulSM_A0;
5568 ULONG ulSM_A1;
5569 ULONG ulSM_A2;
5570 ULONG ulSM_A3;
5571 ULONG ulSM_A4;
5572 ULONG ulSM_A5;
5573 ULONG ulSM_A6;
5574 ULONG ulSM_A7;
5583 ULONG ulMargin_RO_a;
5584 ULONG ulMargin_RO_b;
5585 ULONG ulMargin_RO_c;
5586 ULONG ulMargin_fixed;
5587 ULONG ulMargin_Fmax_mean;
5588 ULONG ulMargin_plat_mean;
5589 ULONG ulMargin_Fmax_sigma;
5590 ULONG ulMargin_plat_sigma;
5591 ULONG ulMargin_DC_sigma;
5592 ULONG ulLoadLineSlop;
5593 ULONG ulaTDClimitPerDPM[8];
5594 ULONG ulaNoCalcVddcPerDPM[8];
5595 ULONG ulAVFS_meanNsigma_Acontant0;
5596 ULONG ulAVFS_meanNsigma_Acontant1;
5597 ULONG ulAVFS_meanNsigma_Acontant2;
5601 ULONG ulGB_VDROOP_TABLE_CKSOFF_a0;
5602 ULONG ulGB_VDROOP_TABLE_CKSOFF_a1;
5603 ULONG ulGB_VDROOP_TABLE_CKSOFF_a2;
5604 ULONG ulGB_VDROOP_TABLE_CKSON_a0;
5605 ULONG ulGB_VDROOP_TABLE_CKSON_a1;
5606 ULONG ulGB_VDROOP_TABLE_CKSON_a2;
5607 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
5609 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_b;
5610 ULONG ulAVFSGB_FUSE_TABLE_CKSON_m1;
5612 ULONG ulAVFSGB_FUSE_TABLE_CKSON_b;
5625 ULONG ulMaxSclkFreq;
5694 …ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same volta…
5695 …ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage …
5702 …ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage …
5707 …ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index,…
5719 ULONG ulBootUpEngineClock;
5720 ULONG ulDentistVCOFreq;
5721 ULONG ulBootUpUMAClock;
5723 ULONG ulBootUpReqDisplayVector;
5724 ULONG ulOtherDisplayMisc;
5725 ULONG ulGPUCapInfo;
5726 ULONG ulSB_MMIO_Base_Addr;
5730 ULONG ulMinEngineClock;
5731 ULONG ulSystemConfig;
5732 ULONG ulCPUCapInfo;
5740 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];
5741 ULONG ulCSR_M3_ARB_CNTL_UVD[10];
5742 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];
5744 ULONG ulGMCRestoreResetTime;
5745 ULONG ulMinimumNClk;
5746 ULONG ulIdleNClk;
5747 ULONG ulDDR_DLL_PowerUpTime;
5748 ULONG ulDDR_PLL_PowerUpTime;
5757 ULONG SclkDpmBoostMargin;
5758 ULONG SclkDpmThrottleMargin;
5761 ULONG ulBoostEngineCLock;
5768 ULONG ulReserved3[15];
5882 ULONG ulPowerplayTable[128];
5889 ULONG uReserved:2;
5890 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
5891 ULONG uCTDP_Value:14; // Override value in tens of milli watts
5892 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5894 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5895 ULONG uCTDP_Value:14; // Override value in tens of milli watts
5896 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts
5897 ULONG uReserved:2;
5904 ULONG TDP_config_all;
5917 ULONG ulBootUpEngineClock;
5918 ULONG ulDentistVCOFreq;
5919 ULONG ulBootUpUMAClock;
5921 ULONG ulBootUpReqDisplayVector;
5922 ULONG ulOtherDisplayMisc;
5923 ULONG ulGPUCapInfo;
5924 ULONG ulSB_MMIO_Base_Addr;
5928 ULONG ulMinEngineClock;
5929 ULONG ulSystemConfig;
5930 ULONG ulCPUCapInfo;
5940 ULONG ulReserved[19];
5942 ULONG ulGMCRestoreResetTime;
5943 ULONG ulMinimumNClk;
5944 ULONG ulIdleNClk;
5945 ULONG ulDDR_DLL_PowerUpTime;
5946 ULONG ulDDR_PLL_PowerUpTime;
5955 ULONG SclkDpmBoostMargin;
5956 ULONG SclkDpmThrottleMargin;
5959 ULONG ulBoostEngineCLock;
5974 ULONG ulLCDBitDepthControlVal;
5975 ULONG ulNbpStateMemclkFreq[4];
5978 ULONG ulNbpStateNClkFreq[4];
6149 ULONG ulBootUpEngineClock;
6150 ULONG ulDentistVCOFreq;
6151 ULONG ulBootUpUMAClock;
6153 ULONG ulBootUpReqDisplayVector;
6154 ULONG ulVBIOSMisc;
6155 ULONG ulGPUCapInfo;
6156 ULONG ulDISP_CLK2Freq;
6160 ULONG ulReserved2;
6161 ULONG ulSystemConfig;
6162 ULONG ulCPUCapInfo;
6163 ULONG ulReserved3;
6171 ULONG ulReserved[19];
6173 ULONG ulGMCRestoreResetTime;
6174 ULONG ulReserved4;
6175 ULONG ulIdleNClk;
6176 ULONG ulDDR_DLL_PowerUpTime;
6177 ULONG ulDDR_PLL_PowerUpTime;
6186 ULONG ulGPUReservedSysMemBaseAddrLo;
6187 ULONG ulGPUReservedSysMemBaseAddrHi;
6189 ULONG ulReserved5;
6201 ULONG ulLCDBitDepthControlVal;
6202 ULONG ulNbpStateMemclkFreq[4];
6203 ULONG ulPSPVersion;
6204 ULONG ulNbpStateNClkFreq[4];
6367 ULONG ulBootUpEngineClock;
6368 ULONG ulDentistVCOFreq;
6369 ULONG ulBootUpUMAClock;
6371 ULONG ulBootUpReqDisplayVector;
6372 ULONG ulVBIOSMisc;
6373 ULONG ulGPUCapInfo;
6374 ULONG ulDISP_CLK2Freq;
6378 ULONG ulReserved2;
6379 ULONG ulSystemConfig;
6380 ULONG ulCPUCapInfo;
6381 ULONG ulReserved3;
6392 ULONG ulReserved[2];
6395 ULONG ulGMCRestoreResetTime;
6396 ULONG ulReserved4;
6397 ULONG ulIdleNClk;
6398 ULONG ulDDR_DLL_PowerUpTime;
6399 ULONG ulDDR_PLL_PowerUpTime;
6408 ULONG ulGPUReservedSysMemBaseAddrLo;
6409 ULONG ulGPUReservedSysMemBaseAddrHi;
6410 ULONG ulReserved5[3];
6422 ULONG ulLCDBitDepthControlVal;
6423 ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed.
6424 ULONG ulPSPVersion;
6425 ULONG ulNbpStateNClkFreq[4];
6457 ULONG ucPara;
6480 ULONG ulVersionCode;
6484 ULONG ulCrcVal; // CRC
6490 ULONG ulBootUpEngineClock;
6491 ULONG ulDentistVCOFreq;
6492 ULONG ulBootUpUMAClock;
6493 ULONG ulReserved0[8];
6494 ULONG ulBootUpReqDisplayVector;
6495 ULONG ulVBIOSMisc;
6496 ULONG ulGPUCapInfo;
6497 ULONG ulReserved1;
6501 ULONG ulReserved2;
6502 ULONG ulSystemConfig;
6503 ULONG ulCPUCapInfo;
6504 ULONG ulReserved3;
6510 ULONG ulMsgReserved[10];
6512 ULONG ulReserved[7];
6514 ULONG ulReserved6[10];
6515 ULONG ulGMCRestoreResetTime;
6516 ULONG ulReserved4;
6517 ULONG ulIdleNClk;
6518 ULONG ulDDR_DLL_PowerUpTime;
6519 ULONG ulDDR_PLL_PowerUpTime;
6528 ULONG ulGPUReservedSysMemBaseAddrLo;
6529 ULONG ulGPUReservedSysMemBaseAddrHi;
6530 ULONG ulReserved5[3];
6542 ULONG ulLCDBitDepthControlVal;
6543 ULONG ulNbpStateMemclkFreq[2];
6544 ULONG ulReserved7[2];
6545 ULONG ulPSPVersion;
6546 ULONG ulNbpStateNClkFreq[4];
6553 ULONG ulReserved8[29];
6561 …ULONG ulPowerplayTable[128]; // Update comments here to link new …
6568 …ULONG ulPowerplayTable[192]; // Reserve 768 bytes space for P…
6613 …ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in…
6638 …ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out …
6669 …ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out …
7153 ULONG ulTargetMemoryClock; //In 10Khz unit
7191 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position
7330 ULONG ulEfuseValue;
7427 ULONG ulDllResetClkRange;
7433 ULONG ucMemBlkId:8;
7434 ULONG ulMemClockRange:24;
7436 ULONG ulMemClockRange:24;
7437 ULONG ucMemBlkId:8;
7444 ULONG ulAccess;
7450 ULONG aulMemData[1];
7472 #define VALUE_DWORD SIZEOF ULONG
7490 ULONG ulARB_SEQDataBuf[32];
7499 ULONG ulRegValue;
7505 ULONG ulMCUcodeVersion;
7506 ULONG ulMCUcodeRomStartAddr;
7507 ULONG ulMCUcodeLength;
7565 ULONG ulSignature;
7583 ULONG ulReserved;
7605 ULONG ulReserved;
7606 …ULONG ulFlags; // To enable/disable functionalities based on mem…
7607 …ULONG ulEngineClock; // Override of default engine clock for particular m…
7608 …ULONG ulMemoryClock; // Override of default memory clock for particular m…
7633 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory…
7669 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memor…
7705 …ULONG ulClkRange; // memory clock in 10kHz unit, when …
7742 …ULONG ulDllDisClock; // memory DLL will be disable when target memory cl…
7769 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination
7791 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7833 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7865 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination
7897 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
7928 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP
7952 ULONG ulChannelMapCfg1; // channel mapping for channel8~15
7953 ULONG ulBankMapCfg;
7954 ULONG ulReserved;
7988 …ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) …
8030 ULONG ulByte0BitRemapCh0;
8031 ULONG ulByte1BitRemapCh0;
8032 ULONG ulByte2BitRemapCh0;
8033 ULONG ulByte3BitRemapCh0;
8034 ULONG ulByte0BitRemapCh1;
8035 ULONG ulByte1BitRemapCh1;
8036 ULONG ulByte2BitRemapCh1;
8037 ULONG ulByte3BitRemapCh1;
8059 ULONG ulMCUcodeVersion;
8122 ULONG Ptr32_Bit;
8167 ULONG RsvdOffScrnMemSize;
8168 ULONG RsvdOffScrnMEmPtr;
8182 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function
8210 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer
8211 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
8226 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode
8506 ULONG ulReserved;
8513 ULONG ulReserved;
8602 ULONG ulAnalogSetting[1];
8611 ULONG ulCondition;
8612 ULONG ulRegVal;
8616 ULONG ulCondition;
8618 ULONG ulRegVal;
8978 ULONG ulMiscInfo; //The power level should be arranged in ascending order
8979 ULONG ulReserved1; // must set to 0
8980 ULONG ulReserved2; // must set to 0
8994 ULONG ulMiscInfo; //The power level should be arranged in ascending order
8995 ULONG ulMiscInfo2;
8996 ULONG ulEngineClock;
8997 ULONG ulMemoryClock;
9009 ULONG ulMiscInfo; //The power level should be arranged in ascending order
9010 ULONG ulMiscInfo2;
9011 ULONG ulEngineClock;
9012 ULONG ulMemoryClock;
9230 ULONG Signature;
9231 ULONG TableLength; //Length
9236 ULONG OemRevision;
9237 ULONG CreatorId;
9238 ULONG CreatorRevision;
9257 …ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of …
9258 …ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of t…
9259 ULONG Reserved[4]; //0x3C
9263 ULONG PCIBus; //0x4C
9264 ULONG PCIDevice; //0x50
9265 ULONG PCIFunction; //0x54
9270 ULONG Revision; //0x60
9271 ULONG ImageLength; //0x64