61 	adev->irq.ih.enabled = true;  in vega10_ih_enable_interrupts()
121 	adev->irq.ih.enabled = false;  in vega10_ih_disable_interrupts()
122 	adev->irq.ih.rptr = 0;  in vega10_ih_disable_interrupts()
166 static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)  in vega10_ih_rb_cntl()  argument
168 	int rb_bufsz = order_base_2(ih->ring_size / 4);  in vega10_ih_rb_cntl()
171 				   MC_SPACE, ih->use_bus_addr ? 1 : 4);  in vega10_ih_rb_cntl()
189 static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)  in vega10_ih_doorbell_rptr()  argument
193 	if (ih->use_doorbell) {  in vega10_ih_doorbell_rptr()
196 						 ih->doorbell_index);  in vega10_ih_doorbell_rptr()
221 	struct amdgpu_ih_ring *ih;  in vega10_ih_irq_init()  local
231 	ih = &adev->irq.ih;  in vega10_ih_irq_init()
233 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);  in vega10_ih_irq_init()
234 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff);  in vega10_ih_irq_init()
238 	ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);  in vega10_ih_irq_init()
239 	if (adev->irq.ih.use_bus_addr) {  in vega10_ih_irq_init()
263 		     lower_32_bits(ih->wptr_addr));  in vega10_ih_irq_init()
265 		     upper_32_bits(ih->wptr_addr) & 0xFFFF);  in vega10_ih_irq_init()
272 		     vega10_ih_doorbell_rptr(ih));  in vega10_ih_irq_init()
274 	ih = &adev->irq.ih1;  in vega10_ih_irq_init()
275 	if (ih->ring_size) {  in vega10_ih_irq_init()
276 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8);  in vega10_ih_irq_init()
278 			     (ih->gpu_addr >> 40) & 0xff);  in vega10_ih_irq_init()
281 		ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);  in vega10_ih_irq_init()
301 			     vega10_ih_doorbell_rptr(ih));  in vega10_ih_irq_init()
304 	ih = &adev->irq.ih2;  in vega10_ih_irq_init()
305 	if (ih->ring_size) {  in vega10_ih_irq_init()
306 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8);  in vega10_ih_irq_init()
308 			     (ih->gpu_addr >> 40) & 0xff);  in vega10_ih_irq_init()
311 		ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);  in vega10_ih_irq_init()
328 			     vega10_ih_doorbell_rptr(ih));  in vega10_ih_irq_init()
374 			      struct amdgpu_ih_ring *ih)  in vega10_ih_get_wptr()  argument
378 	wptr = le32_to_cpu(*ih->wptr_cpu);  in vega10_ih_get_wptr()
385 	if (ih == &adev->irq.ih)  in vega10_ih_get_wptr()
387 	else if (ih == &adev->irq.ih1)  in vega10_ih_get_wptr()
389 	else if (ih == &adev->irq.ih2)  in vega10_ih_get_wptr()
404 	tmp = (wptr + 32) & ih->ptr_mask;  in vega10_ih_get_wptr()
407 		 wptr, ih->rptr, tmp);  in vega10_ih_get_wptr()
408 	ih->rptr = tmp;  in vega10_ih_get_wptr()
410 	if (ih == &adev->irq.ih)  in vega10_ih_get_wptr()
412 	else if (ih == &adev->irq.ih1)  in vega10_ih_get_wptr()
414 	else if (ih == &adev->irq.ih2)  in vega10_ih_get_wptr()
424 	return (wptr & ih->ptr_mask);  in vega10_ih_get_wptr()
436 				struct amdgpu_ih_ring *ih,  in vega10_ih_decode_iv()  argument
440 	u32 ring_index = ih->rptr >> 2;  in vega10_ih_decode_iv()
443 	dw[0] = le32_to_cpu(ih->ring[ring_index + 0]);  in vega10_ih_decode_iv()
444 	dw[1] = le32_to_cpu(ih->ring[ring_index + 1]);  in vega10_ih_decode_iv()
445 	dw[2] = le32_to_cpu(ih->ring[ring_index + 2]);  in vega10_ih_decode_iv()
446 	dw[3] = le32_to_cpu(ih->ring[ring_index + 3]);  in vega10_ih_decode_iv()
447 	dw[4] = le32_to_cpu(ih->ring[ring_index + 4]);  in vega10_ih_decode_iv()
448 	dw[5] = le32_to_cpu(ih->ring[ring_index + 5]);  in vega10_ih_decode_iv()
449 	dw[6] = le32_to_cpu(ih->ring[ring_index + 6]);  in vega10_ih_decode_iv()
450 	dw[7] = le32_to_cpu(ih->ring[ring_index + 7]);  in vega10_ih_decode_iv()
467 	ih->rptr += 32;  in vega10_ih_decode_iv()
477 			       struct amdgpu_ih_ring *ih)  in vega10_ih_irq_rearm()  argument
483 	if (ih == &adev->irq.ih)  in vega10_ih_irq_rearm()
485 	else if (ih == &adev->irq.ih1)  in vega10_ih_irq_rearm()
487 	else if (ih == &adev->irq.ih2)  in vega10_ih_irq_rearm()
495 		if ((v < ih->ring_size) && (v != ih->rptr))  in vega10_ih_irq_rearm()
496 			WDOORBELL32(ih->doorbell_index, ih->rptr);  in vega10_ih_irq_rearm()
510 			       struct amdgpu_ih_ring *ih)  in vega10_ih_set_rptr()  argument
512 	if (ih->use_doorbell) {  in vega10_ih_set_rptr()
514 		*ih->rptr_cpu = ih->rptr;  in vega10_ih_set_rptr()
515 		WDOORBELL32(ih->doorbell_index, ih->rptr);  in vega10_ih_set_rptr()
518 			vega10_ih_irq_rearm(adev, ih);  in vega10_ih_set_rptr()
519 	} else if (ih == &adev->irq.ih) {  in vega10_ih_set_rptr()
520 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);  in vega10_ih_set_rptr()
521 	} else if (ih == &adev->irq.ih1) {  in vega10_ih_set_rptr()
522 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr);  in vega10_ih_set_rptr()
523 	} else if (ih == &adev->irq.ih2) {  in vega10_ih_set_rptr()
524 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr);  in vega10_ih_set_rptr()
586 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);  in vega10_ih_sw_init()
590 	adev->irq.ih.use_doorbell = true;  in vega10_ih_sw_init()
591 	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;  in vega10_ih_sw_init()
598 	adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;  in vega10_ih_sw_init()
605 	adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;  in vega10_ih_sw_init()
619 	amdgpu_ih_ring_fini(adev, &adev->irq.ih);  in vega10_ih_sw_fini()