Lines Matching refs:vcn
79 adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS; in vcn_v2_5_early_init()
80 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_early_init()
83 adev->vcn.harvest_config |= 1 << i; in vcn_v2_5_early_init()
86 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | in vcn_v2_5_early_init()
91 adev->vcn.num_vcn_inst = 1; in vcn_v2_5_early_init()
93 adev->vcn.num_enc_rings = 2; in vcn_v2_5_early_init()
116 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()
117 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_sw_init()
121 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq); in vcn_v2_5_sw_init()
126 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_sw_init()
128 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq); in vcn_v2_5_sw_init()
135 VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst[j].irq); in vcn_v2_5_sw_init()
146 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; in vcn_v2_5_sw_init()
148 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; in vcn_v2_5_sw_init()
152 if (adev->vcn.num_vcn_inst == VCN25_MAX_HW_INSTANCES_ARCTURUS) { in vcn_v2_5_sw_init()
154 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; in vcn_v2_5_sw_init()
165 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()
166 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_sw_init()
168 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
169 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
170 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
171 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
172 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
173 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
175 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
176 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(UVD, j, mmUVD_SCRATCH9); in vcn_v2_5_sw_init()
177 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
178 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_5_sw_init()
179 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
180 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_5_sw_init()
181 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
182 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_5_sw_init()
183 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
184 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(UVD, j, mmUVD_NO_OP); in vcn_v2_5_sw_init()
186 adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; in vcn_v2_5_sw_init()
187 adev->vcn.inst[j].external.jpeg_pitch = SOC15_REG_OFFSET(UVD, j, mmUVD_JPEG_PITCH); in vcn_v2_5_sw_init()
189 ring = &adev->vcn.inst[j].ring_dec; in vcn_v2_5_sw_init()
191 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8*j; in vcn_v2_5_sw_init()
193 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0); in vcn_v2_5_sw_init()
197 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_sw_init()
198 ring = &adev->vcn.inst[j].ring_enc[i]; in vcn_v2_5_sw_init()
200 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i + 8*j; in vcn_v2_5_sw_init()
202 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0); in vcn_v2_5_sw_init()
207 ring = &adev->vcn.inst[j].ring_jpeg; in vcn_v2_5_sw_init()
209 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8*j; in vcn_v2_5_sw_init()
211 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0); in vcn_v2_5_sw_init()
253 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in vcn_v2_5_hw_init()
254 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_hw_init()
256 ring = &adev->vcn.inst[j].ring_dec; in vcn_v2_5_hw_init()
267 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_hw_init()
268 ring = &adev->vcn.inst[j].ring_enc[i]; in vcn_v2_5_hw_init()
278 ring = &adev->vcn.inst[j].ring_jpeg; in vcn_v2_5_hw_init()
305 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_hw_fini()
306 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_hw_fini()
308 ring = &adev->vcn.inst[i].ring_dec; in vcn_v2_5_hw_fini()
315 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_hw_fini()
316 ring = &adev->vcn.inst[i].ring_enc[i]; in vcn_v2_5_hw_fini()
320 ring = &adev->vcn.inst[i].ring_jpeg; in vcn_v2_5_hw_fini()
378 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_5_mc_resume()
382 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_mc_resume()
383 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_mc_resume()
395 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
397 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
406 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
408 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
414 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
416 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
436 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_disable_clock_gating()
437 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_disable_clock_gating()
554 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_enable_clock_gating()
555 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_enable_clock_gating()
617 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in jpeg_v2_5_start()
618 if (adev->vcn.harvest_config & (1 << i)) in jpeg_v2_5_start()
620 ring = &adev->vcn.inst[i].ring_jpeg; in jpeg_v2_5_start()
689 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in jpeg_v2_5_stop()
690 if (adev->vcn.harvest_config & (1 << i)) in jpeg_v2_5_stop()
719 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_start()
720 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_start()
734 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_start()
735 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_start()
783 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_start()
784 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_start()
847 ring = &adev->vcn.inst[i].ring_dec; in vcn_v2_5_start()
869 ring = &adev->vcn.inst[i].ring_enc[0]; in vcn_v2_5_start()
876 ring = &adev->vcn.inst[i].ring_enc[1]; in vcn_v2_5_start()
897 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_stop()
898 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_stop()
1043 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) in vcn_v2_5_enc_ring_get_rptr()
1060 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { in vcn_v2_5_enc_ring_get_wptr()
1084 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { in vcn_v2_5_enc_ring_set_wptr()
1215 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_set_dec_ring_funcs()
1216 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_set_dec_ring_funcs()
1218 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs; in vcn_v2_5_set_dec_ring_funcs()
1219 adev->vcn.inst[i].ring_dec.me = i; in vcn_v2_5_set_dec_ring_funcs()
1228 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in vcn_v2_5_set_enc_ring_funcs()
1229 if (adev->vcn.harvest_config & (1 << j)) in vcn_v2_5_set_enc_ring_funcs()
1231 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_5_set_enc_ring_funcs()
1232 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs; in vcn_v2_5_set_enc_ring_funcs()
1233 adev->vcn.inst[j].ring_enc[i].me = j; in vcn_v2_5_set_enc_ring_funcs()
1243 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_set_jpeg_ring_funcs()
1244 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_set_jpeg_ring_funcs()
1246 adev->vcn.inst[i].ring_jpeg.funcs = &vcn_v2_5_jpeg_ring_vm_funcs; in vcn_v2_5_set_jpeg_ring_funcs()
1247 adev->vcn.inst[i].ring_jpeg.me = i; in vcn_v2_5_set_jpeg_ring_funcs()
1257 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_is_idle()
1258 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_is_idle()
1271 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_wait_for_idle()
1272 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_wait_for_idle()
1306 if(state == adev->vcn.cur_state) in vcn_v2_5_set_powergating_state()
1315 adev->vcn.cur_state = state; in vcn_v2_5_set_powergating_state()
1350 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); in vcn_v2_5_process_interrupt()
1353 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); in vcn_v2_5_process_interrupt()
1356 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); in vcn_v2_5_process_interrupt()
1359 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_jpeg); in vcn_v2_5_process_interrupt()
1379 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_set_irq_funcs()
1380 if (adev->vcn.harvest_config & (1 << i)) in vcn_v2_5_set_irq_funcs()
1382 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 2; in vcn_v2_5_set_irq_funcs()
1383 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs; in vcn_v2_5_set_irq_funcs()