Lines Matching refs:vcn
95 adev->vcn.num_vcn_inst = 1; in vcn_v2_0_early_init()
96 adev->vcn.num_enc_rings = 2; in vcn_v2_0_early_init()
122 &adev->vcn.inst->irq); in vcn_v2_0_sw_init()
127 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_0_sw_init()
130 &adev->vcn.inst->irq); in vcn_v2_0_sw_init()
137 VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst->irq); in vcn_v2_0_sw_init()
147 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; in vcn_v2_0_sw_init()
149 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; in vcn_v2_0_sw_init()
159 ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_sw_init()
162 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; in vcn_v2_0_sw_init()
165 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); in vcn_v2_0_sw_init()
169 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
170 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
171 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
172 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
173 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
174 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
176 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
177 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); in vcn_v2_0_sw_init()
178 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
179 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_0_sw_init()
180 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
181 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_0_sw_init()
182 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
183 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_0_sw_init()
184 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
185 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); in vcn_v2_0_sw_init()
187 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_0_sw_init()
188 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v2_0_sw_init()
190 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; in vcn_v2_0_sw_init()
192 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); in vcn_v2_0_sw_init()
197 ring = &adev->vcn.inst->ring_jpeg; in vcn_v2_0_sw_init()
199 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; in vcn_v2_0_sw_init()
201 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); in vcn_v2_0_sw_init()
205 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode; in vcn_v2_0_sw_init()
207 adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
208 adev->vcn.inst->external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH); in vcn_v2_0_sw_init()
244 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_hw_init()
257 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_0_hw_init()
258 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v2_0_hw_init()
267 ring = &adev->vcn.inst->ring_jpeg; in vcn_v2_0_hw_init()
293 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_hw_fini()
297 (adev->vcn.cur_state != AMD_PG_STATE_GATE && in vcn_v2_0_hw_fini()
303 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v2_0_hw_fini()
304 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v2_0_hw_fini()
308 ring = &adev->vcn.inst->ring_jpeg; in vcn_v2_0_hw_fini()
365 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_mc_resume()
378 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
380 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
390 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
392 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
398 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
400 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
410 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v2_0_mc_resume_dpg_mode()
436 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
439 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
457 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
460 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
477 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
480 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
668 struct amdgpu_ring *ring = &adev->vcn.inst->ring_jpeg; in jpeg_v2_0_start()
930 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_start_dpg_mode()
942 adev->vcn.dpg_sram_curr_addr = (uint32_t*)adev->vcn.dpg_sram_cpu_addr; in vcn_v2_0_start_dpg_mode()
1016 psp_update_vcn_sram(adev, 0, adev->vcn.dpg_sram_gpu_addr, in vcn_v2_0_start_dpg_mode()
1017 (uint32_t)((uintptr_t)adev->vcn.dpg_sram_curr_addr - in vcn_v2_0_start_dpg_mode()
1018 (uintptr_t)adev->vcn.dpg_sram_cpu_addr)); in vcn_v2_0_start_dpg_mode()
1056 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_start()
1065 r = vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram); in vcn_v2_0_start()
1207 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v2_0_start()
1214 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v2_0_start()
1339 if (adev->vcn.pause_state.fw_based != new_state->fw_based) { in vcn_v2_0_pause_dpg_mode()
1341 adev->vcn.pause_state.fw_based, new_state->fw_based); in vcn_v2_0_pause_dpg_mode()
1361 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v2_0_pause_dpg_mode()
1368 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v2_0_pause_dpg_mode()
1387 adev->vcn.pause_state.fw_based = new_state->fw_based; in vcn_v2_0_pause_dpg_mode()
1494 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_insert_start()
1496 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_start()
1511 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_end()
1530 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); in vcn_v2_0_dec_ring_insert_nop()
1549 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); in vcn_v2_0_dec_ring_emit_fence()
1552 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence()
1555 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_fence()
1558 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_fence()
1561 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence()
1564 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_fence()
1567 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_fence()
1588 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0)); in vcn_v2_0_dec_ring_emit_ib()
1591 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0)); in vcn_v2_0_dec_ring_emit_ib()
1593 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0)); in vcn_v2_0_dec_ring_emit_ib()
1595 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0)); in vcn_v2_0_dec_ring_emit_ib()
1604 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1607 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1610 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1613 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1638 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1641 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1644 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1660 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v2_0_enc_ring_get_rptr()
1677 if (ring == &adev->vcn.inst->ring_enc[0]) { in vcn_v2_0_enc_ring_get_wptr()
1701 if (ring == &adev->vcn.inst->ring_enc[0]) { in vcn_v2_0_enc_ring_set_wptr()
2075 amdgpu_fence_process(&adev->vcn.inst->ring_dec); in vcn_v2_0_process_interrupt()
2078 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); in vcn_v2_0_process_interrupt()
2081 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); in vcn_v2_0_process_interrupt()
2084 amdgpu_fence_process(&adev->vcn.inst->ring_jpeg); in vcn_v2_0_process_interrupt()
2102 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); in vcn_v2_0_dec_ring_test_ring()
2106 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_test_ring()
2108 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); in vcn_v2_0_dec_ring_test_ring()
2112 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); in vcn_v2_0_dec_ring_test_ring()
2138 if (state == adev->vcn.cur_state) in vcn_v2_0_set_powergating_state()
2147 adev->vcn.cur_state = state; in vcn_v2_0_set_powergating_state()
2263 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs; in vcn_v2_0_set_dec_ring_funcs()
2271 for (i = 0; i < adev->vcn.num_enc_rings; ++i) in vcn_v2_0_set_enc_ring_funcs()
2272 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs; in vcn_v2_0_set_enc_ring_funcs()
2279 adev->vcn.inst->ring_jpeg.funcs = &vcn_v2_0_jpeg_ring_vm_funcs; in vcn_v2_0_set_jpeg_ring_funcs()
2290 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; in vcn_v2_0_set_irq_funcs()
2291 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs; in vcn_v2_0_set_irq_funcs()