Lines Matching refs:ring
115 struct amdgpu_ring *ring; in vcn_v2_0_sw_init() local
159 ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_sw_init()
161 ring->use_doorbell = true; in vcn_v2_0_sw_init()
162 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; in vcn_v2_0_sw_init()
164 sprintf(ring->name, "vcn_dec"); in vcn_v2_0_sw_init()
165 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); in vcn_v2_0_sw_init()
188 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v2_0_sw_init()
189 ring->use_doorbell = true; in vcn_v2_0_sw_init()
190 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; in vcn_v2_0_sw_init()
191 sprintf(ring->name, "vcn_enc%d", i); in vcn_v2_0_sw_init()
192 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); in vcn_v2_0_sw_init()
197 ring = &adev->vcn.inst->ring_jpeg; in vcn_v2_0_sw_init()
198 ring->use_doorbell = true; in vcn_v2_0_sw_init()
199 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; in vcn_v2_0_sw_init()
200 sprintf(ring->name, "vcn_jpeg"); in vcn_v2_0_sw_init()
201 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); in vcn_v2_0_sw_init()
244 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_hw_init() local
247 adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell, in vcn_v2_0_hw_init()
248 ring->doorbell_index, 0); in vcn_v2_0_hw_init()
250 ring->sched.ready = true; in vcn_v2_0_hw_init()
251 r = amdgpu_ring_test_ring(ring); in vcn_v2_0_hw_init()
253 ring->sched.ready = false; in vcn_v2_0_hw_init()
258 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v2_0_hw_init()
259 ring->sched.ready = true; in vcn_v2_0_hw_init()
260 r = amdgpu_ring_test_ring(ring); in vcn_v2_0_hw_init()
262 ring->sched.ready = false; in vcn_v2_0_hw_init()
267 ring = &adev->vcn.inst->ring_jpeg; in vcn_v2_0_hw_init()
268 ring->sched.ready = true; in vcn_v2_0_hw_init()
269 r = amdgpu_ring_test_ring(ring); in vcn_v2_0_hw_init()
271 ring->sched.ready = false; in vcn_v2_0_hw_init()
293 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_hw_fini() local
301 ring->sched.ready = false; in vcn_v2_0_hw_fini()
304 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v2_0_hw_fini()
305 ring->sched.ready = false; in vcn_v2_0_hw_fini()
308 ring = &adev->vcn.inst->ring_jpeg; in vcn_v2_0_hw_fini()
309 ring->sched.ready = false; in vcn_v2_0_hw_fini()
668 struct amdgpu_ring *ring = &adev->vcn.inst->ring_jpeg; in jpeg_v2_0_start() local
716 lower_32_bits(ring->gpu_addr)); in jpeg_v2_0_start()
718 upper_32_bits(ring->gpu_addr)); in jpeg_v2_0_start()
722 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); in jpeg_v2_0_start()
723 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); in jpeg_v2_0_start()
930 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_start_dpg_mode() local
1021 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start_dpg_mode()
1034 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_0_start_dpg_mode()
1038 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
1040 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
1047 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v2_0_start_dpg_mode()
1049 lower_32_bits(ring->wptr)); in vcn_v2_0_start_dpg_mode()
1056 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v2_0_start() local
1186 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start()
1196 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1198 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1203 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v2_0_start()
1205 lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1207 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v2_0_start()
1208 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1209 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1210 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_start()
1211 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1212 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_0_start()
1214 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v2_0_start()
1215 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1216 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1217 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_0_start()
1218 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1219 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_0_start()
1334 struct amdgpu_ring *ring; in vcn_v2_0_pause_dpg_mode() local
1361 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v2_0_pause_dpg_mode()
1362 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
1363 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_pause_dpg_mode()
1364 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_0_pause_dpg_mode()
1365 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1366 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1368 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v2_0_pause_dpg_mode()
1369 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
1370 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_pause_dpg_mode()
1371 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_0_pause_dpg_mode()
1372 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1373 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1436 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) in vcn_v2_0_dec_ring_get_rptr() argument
1438 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_dec_ring_get_rptr()
1450 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) in vcn_v2_0_dec_ring_get_wptr() argument
1452 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_dec_ring_get_wptr()
1454 if (ring->use_doorbell) in vcn_v2_0_dec_ring_get_wptr()
1455 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_dec_ring_get_wptr()
1467 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) in vcn_v2_0_dec_ring_set_wptr() argument
1469 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_dec_ring_set_wptr()
1473 lower_32_bits(ring->wptr) | 0x80000000); in vcn_v2_0_dec_ring_set_wptr()
1475 if (ring->use_doorbell) { in vcn_v2_0_dec_ring_set_wptr()
1476 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_dec_ring_set_wptr()
1477 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vcn_v2_0_dec_ring_set_wptr()
1479 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_dec_ring_set_wptr()
1490 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) in vcn_v2_0_dec_ring_insert_start() argument
1492 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_dec_ring_insert_start()
1494 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_insert_start()
1495 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_start()
1496 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_start()
1497 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); in vcn_v2_0_dec_ring_insert_start()
1507 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) in vcn_v2_0_dec_ring_insert_end() argument
1509 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_dec_ring_insert_end()
1511 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_insert_end()
1512 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); in vcn_v2_0_dec_ring_insert_end()
1522 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) in vcn_v2_0_dec_ring_insert_nop() argument
1524 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_dec_ring_insert_nop()
1527 WARN_ON(ring->wptr % 2 || count % 2); in vcn_v2_0_dec_ring_insert_nop()
1530 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); in vcn_v2_0_dec_ring_insert_nop()
1531 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_insert_nop()
1543 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, in vcn_v2_0_dec_ring_emit_fence() argument
1546 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_dec_ring_emit_fence()
1549 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); in vcn_v2_0_dec_ring_emit_fence()
1550 amdgpu_ring_write(ring, seq); in vcn_v2_0_dec_ring_emit_fence()
1552 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence()
1553 amdgpu_ring_write(ring, addr & 0xffffffff); in vcn_v2_0_dec_ring_emit_fence()
1555 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_fence()
1556 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); in vcn_v2_0_dec_ring_emit_fence()
1558 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_fence()
1559 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1)); in vcn_v2_0_dec_ring_emit_fence()
1561 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_fence()
1562 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_emit_fence()
1564 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_fence()
1565 amdgpu_ring_write(ring, 0); in vcn_v2_0_dec_ring_emit_fence()
1567 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_fence()
1569 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1)); in vcn_v2_0_dec_ring_emit_fence()
1580 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, in vcn_v2_0_dec_ring_emit_ib() argument
1585 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_dec_ring_emit_ib()
1588 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0)); in vcn_v2_0_dec_ring_emit_ib()
1589 amdgpu_ring_write(ring, vmid); in vcn_v2_0_dec_ring_emit_ib()
1591 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0)); in vcn_v2_0_dec_ring_emit_ib()
1592 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_v2_0_dec_ring_emit_ib()
1593 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0)); in vcn_v2_0_dec_ring_emit_ib()
1594 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_v2_0_dec_ring_emit_ib()
1595 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0)); in vcn_v2_0_dec_ring_emit_ib()
1596 amdgpu_ring_write(ring, ib->length_dw); in vcn_v2_0_dec_ring_emit_ib()
1599 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, in vcn_v2_0_dec_ring_emit_reg_wait() argument
1602 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_dec_ring_emit_reg_wait()
1604 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1605 amdgpu_ring_write(ring, reg << 2); in vcn_v2_0_dec_ring_emit_reg_wait()
1607 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1608 amdgpu_ring_write(ring, val); in vcn_v2_0_dec_ring_emit_reg_wait()
1610 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1611 amdgpu_ring_write(ring, mask); in vcn_v2_0_dec_ring_emit_reg_wait()
1613 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_reg_wait()
1615 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1)); in vcn_v2_0_dec_ring_emit_reg_wait()
1618 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, in vcn_v2_0_dec_ring_emit_vm_flush() argument
1621 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; in vcn_v2_0_dec_ring_emit_vm_flush()
1624 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in vcn_v2_0_dec_ring_emit_vm_flush()
1630 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); in vcn_v2_0_dec_ring_emit_vm_flush()
1633 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, in vcn_v2_0_dec_ring_emit_wreg() argument
1636 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_dec_ring_emit_wreg()
1638 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1639 amdgpu_ring_write(ring, reg << 2); in vcn_v2_0_dec_ring_emit_wreg()
1641 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1642 amdgpu_ring_write(ring, val); in vcn_v2_0_dec_ring_emit_wreg()
1644 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_emit_wreg()
1646 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1)); in vcn_v2_0_dec_ring_emit_wreg()
1656 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring) in vcn_v2_0_enc_ring_get_rptr() argument
1658 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_enc_ring_get_rptr()
1660 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v2_0_enc_ring_get_rptr()
1673 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring) in vcn_v2_0_enc_ring_get_wptr() argument
1675 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_enc_ring_get_wptr()
1677 if (ring == &adev->vcn.inst->ring_enc[0]) { in vcn_v2_0_enc_ring_get_wptr()
1678 if (ring->use_doorbell) in vcn_v2_0_enc_ring_get_wptr()
1679 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_enc_ring_get_wptr()
1683 if (ring->use_doorbell) in vcn_v2_0_enc_ring_get_wptr()
1684 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_enc_ring_get_wptr()
1697 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring) in vcn_v2_0_enc_ring_set_wptr() argument
1699 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_enc_ring_set_wptr()
1701 if (ring == &adev->vcn.inst->ring_enc[0]) { in vcn_v2_0_enc_ring_set_wptr()
1702 if (ring->use_doorbell) { in vcn_v2_0_enc_ring_set_wptr()
1703 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_enc_ring_set_wptr()
1704 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vcn_v2_0_enc_ring_set_wptr()
1706 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_enc_ring_set_wptr()
1709 if (ring->use_doorbell) { in vcn_v2_0_enc_ring_set_wptr()
1710 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_enc_ring_set_wptr()
1711 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vcn_v2_0_enc_ring_set_wptr()
1713 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_enc_ring_set_wptr()
1726 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, in vcn_v2_0_enc_ring_emit_fence() argument
1731 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); in vcn_v2_0_enc_ring_emit_fence()
1732 amdgpu_ring_write(ring, addr); in vcn_v2_0_enc_ring_emit_fence()
1733 amdgpu_ring_write(ring, upper_32_bits(addr)); in vcn_v2_0_enc_ring_emit_fence()
1734 amdgpu_ring_write(ring, seq); in vcn_v2_0_enc_ring_emit_fence()
1735 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); in vcn_v2_0_enc_ring_emit_fence()
1738 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring) in vcn_v2_0_enc_ring_insert_end() argument
1740 amdgpu_ring_write(ring, VCN_ENC_CMD_END); in vcn_v2_0_enc_ring_insert_end()
1751 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, in vcn_v2_0_enc_ring_emit_ib() argument
1758 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); in vcn_v2_0_enc_ring_emit_ib()
1759 amdgpu_ring_write(ring, vmid); in vcn_v2_0_enc_ring_emit_ib()
1760 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_v2_0_enc_ring_emit_ib()
1761 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_v2_0_enc_ring_emit_ib()
1762 amdgpu_ring_write(ring, ib->length_dw); in vcn_v2_0_enc_ring_emit_ib()
1765 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, in vcn_v2_0_enc_ring_emit_reg_wait() argument
1768 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); in vcn_v2_0_enc_ring_emit_reg_wait()
1769 amdgpu_ring_write(ring, reg << 2); in vcn_v2_0_enc_ring_emit_reg_wait()
1770 amdgpu_ring_write(ring, mask); in vcn_v2_0_enc_ring_emit_reg_wait()
1771 amdgpu_ring_write(ring, val); in vcn_v2_0_enc_ring_emit_reg_wait()
1774 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, in vcn_v2_0_enc_ring_emit_vm_flush() argument
1777 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; in vcn_v2_0_enc_ring_emit_vm_flush()
1779 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in vcn_v2_0_enc_ring_emit_vm_flush()
1782 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, in vcn_v2_0_enc_ring_emit_vm_flush()
1786 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) in vcn_v2_0_enc_ring_emit_wreg() argument
1788 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); in vcn_v2_0_enc_ring_emit_wreg()
1789 amdgpu_ring_write(ring, reg << 2); in vcn_v2_0_enc_ring_emit_wreg()
1790 amdgpu_ring_write(ring, val); in vcn_v2_0_enc_ring_emit_wreg()
1800 static uint64_t vcn_v2_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring) in vcn_v2_0_jpeg_ring_get_rptr() argument
1802 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_jpeg_ring_get_rptr()
1814 static uint64_t vcn_v2_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring) in vcn_v2_0_jpeg_ring_get_wptr() argument
1816 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_jpeg_ring_get_wptr()
1818 if (ring->use_doorbell) in vcn_v2_0_jpeg_ring_get_wptr()
1819 return adev->wb.wb[ring->wptr_offs]; in vcn_v2_0_jpeg_ring_get_wptr()
1831 static void vcn_v2_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring) in vcn_v2_0_jpeg_ring_set_wptr() argument
1833 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_jpeg_ring_set_wptr()
1835 if (ring->use_doorbell) { in vcn_v2_0_jpeg_ring_set_wptr()
1836 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vcn_v2_0_jpeg_ring_set_wptr()
1837 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vcn_v2_0_jpeg_ring_set_wptr()
1839 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_jpeg_ring_set_wptr()
1850 void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring) in vcn_v2_0_jpeg_ring_insert_start() argument
1852 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_insert_start()
1854 amdgpu_ring_write(ring, 0x68e04); in vcn_v2_0_jpeg_ring_insert_start()
1856 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in vcn_v2_0_jpeg_ring_insert_start()
1858 amdgpu_ring_write(ring, 0x80010000); in vcn_v2_0_jpeg_ring_insert_start()
1868 void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring) in vcn_v2_0_jpeg_ring_insert_end() argument
1870 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_insert_end()
1872 amdgpu_ring_write(ring, 0x68e04); in vcn_v2_0_jpeg_ring_insert_end()
1874 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in vcn_v2_0_jpeg_ring_insert_end()
1876 amdgpu_ring_write(ring, 0x00010000); in vcn_v2_0_jpeg_ring_insert_end()
1887 void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, in vcn_v2_0_jpeg_ring_emit_fence() argument
1892 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_fence()
1894 amdgpu_ring_write(ring, seq); in vcn_v2_0_jpeg_ring_emit_fence()
1896 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_fence()
1898 amdgpu_ring_write(ring, seq); in vcn_v2_0_jpeg_ring_emit_fence()
1900 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_fence()
1902 amdgpu_ring_write(ring, lower_32_bits(addr)); in vcn_v2_0_jpeg_ring_emit_fence()
1904 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_fence()
1906 amdgpu_ring_write(ring, upper_32_bits(addr)); in vcn_v2_0_jpeg_ring_emit_fence()
1908 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_fence()
1910 amdgpu_ring_write(ring, 0x8); in vcn_v2_0_jpeg_ring_emit_fence()
1912 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_fence()
1914 amdgpu_ring_write(ring, 0); in vcn_v2_0_jpeg_ring_emit_fence()
1916 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_fence()
1918 amdgpu_ring_write(ring, 0x3fbc); in vcn_v2_0_jpeg_ring_emit_fence()
1920 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in vcn_v2_0_jpeg_ring_emit_fence()
1922 amdgpu_ring_write(ring, 0x1); in vcn_v2_0_jpeg_ring_emit_fence()
1924 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); in vcn_v2_0_jpeg_ring_emit_fence()
1925 amdgpu_ring_write(ring, 0); in vcn_v2_0_jpeg_ring_emit_fence()
1936 void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, in vcn_v2_0_jpeg_ring_emit_ib() argument
1943 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_ib()
1945 amdgpu_ring_write(ring, (vmid | (vmid << 4))); in vcn_v2_0_jpeg_ring_emit_ib()
1947 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_ib()
1949 amdgpu_ring_write(ring, (vmid | (vmid << 4))); in vcn_v2_0_jpeg_ring_emit_ib()
1951 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_ib()
1953 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_v2_0_jpeg_ring_emit_ib()
1955 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_ib()
1957 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_v2_0_jpeg_ring_emit_ib()
1959 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_ib()
1961 amdgpu_ring_write(ring, ib->length_dw); in vcn_v2_0_jpeg_ring_emit_ib()
1963 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_ib()
1965 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); in vcn_v2_0_jpeg_ring_emit_ib()
1967 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_ib()
1969 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_jpeg_ring_emit_ib()
1971 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); in vcn_v2_0_jpeg_ring_emit_ib()
1972 amdgpu_ring_write(ring, 0); in vcn_v2_0_jpeg_ring_emit_ib()
1974 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_ib()
1976 amdgpu_ring_write(ring, 0x01400200); in vcn_v2_0_jpeg_ring_emit_ib()
1978 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_ib()
1980 amdgpu_ring_write(ring, 0x2); in vcn_v2_0_jpeg_ring_emit_ib()
1982 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_ib()
1984 amdgpu_ring_write(ring, 0x2); in vcn_v2_0_jpeg_ring_emit_ib()
1987 void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, in vcn_v2_0_jpeg_ring_emit_reg_wait() argument
1992 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_reg_wait()
1994 amdgpu_ring_write(ring, 0x01400200); in vcn_v2_0_jpeg_ring_emit_reg_wait()
1996 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_reg_wait()
1998 amdgpu_ring_write(ring, val); in vcn_v2_0_jpeg_ring_emit_reg_wait()
2000 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_reg_wait()
2003 amdgpu_ring_write(ring, 0); in vcn_v2_0_jpeg_ring_emit_reg_wait()
2004 amdgpu_ring_write(ring, in vcn_v2_0_jpeg_ring_emit_reg_wait()
2007 amdgpu_ring_write(ring, reg_offset); in vcn_v2_0_jpeg_ring_emit_reg_wait()
2008 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in vcn_v2_0_jpeg_ring_emit_reg_wait()
2011 amdgpu_ring_write(ring, mask); in vcn_v2_0_jpeg_ring_emit_reg_wait()
2014 void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring, in vcn_v2_0_jpeg_ring_emit_vm_flush() argument
2017 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; in vcn_v2_0_jpeg_ring_emit_vm_flush()
2020 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in vcn_v2_0_jpeg_ring_emit_vm_flush()
2026 vcn_v2_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask); in vcn_v2_0_jpeg_ring_emit_vm_flush()
2029 void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) in vcn_v2_0_jpeg_ring_emit_wreg() argument
2033 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, in vcn_v2_0_jpeg_ring_emit_wreg()
2036 amdgpu_ring_write(ring, 0); in vcn_v2_0_jpeg_ring_emit_wreg()
2037 amdgpu_ring_write(ring, in vcn_v2_0_jpeg_ring_emit_wreg()
2040 amdgpu_ring_write(ring, reg_offset); in vcn_v2_0_jpeg_ring_emit_wreg()
2041 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, in vcn_v2_0_jpeg_ring_emit_wreg()
2044 amdgpu_ring_write(ring, val); in vcn_v2_0_jpeg_ring_emit_wreg()
2047 void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count) in vcn_v2_0_jpeg_ring_nop() argument
2051 WARN_ON(ring->wptr % 2 || count % 2); in vcn_v2_0_jpeg_ring_nop()
2054 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in vcn_v2_0_jpeg_ring_nop()
2055 amdgpu_ring_write(ring, 0); in vcn_v2_0_jpeg_ring_nop()
2095 static int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring) in vcn_v2_0_dec_ring_test_ring() argument
2097 struct amdgpu_device *adev = ring->adev; in vcn_v2_0_dec_ring_test_ring()
2102 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); in vcn_v2_0_dec_ring_test_ring()
2103 r = amdgpu_ring_alloc(ring, 4); in vcn_v2_0_dec_ring_test_ring()
2106 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); in vcn_v2_0_dec_ring_test_ring()
2107 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); in vcn_v2_0_dec_ring_test_ring()
2108 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); in vcn_v2_0_dec_ring_test_ring()
2109 amdgpu_ring_write(ring, 0xDEADBEEF); in vcn_v2_0_dec_ring_test_ring()
2110 amdgpu_ring_commit(ring); in vcn_v2_0_dec_ring_test_ring()
2112 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); in vcn_v2_0_dec_ring_test_ring()