178 	adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;  in vcn_v2_0_sw_init()
179 	adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);  in vcn_v2_0_sw_init()
1494 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_insert_start()
1552 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_emit_fence()
1561 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_emit_fence()
1604 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_emit_reg_wait()
1622 	uint32_t data0, data1, mask;  in vcn_v2_0_dec_ring_emit_vm_flush()  local
1627 	data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;  in vcn_v2_0_dec_ring_emit_vm_flush()
1630 	vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);  in vcn_v2_0_dec_ring_emit_vm_flush()
1638 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));  in vcn_v2_0_dec_ring_emit_wreg()
2018 	uint32_t data0, data1, mask;  in vcn_v2_0_jpeg_ring_emit_vm_flush()  local
2023 	data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;  in vcn_v2_0_jpeg_ring_emit_vm_flush()
2026 	vcn_v2_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);  in vcn_v2_0_jpeg_ring_emit_vm_flush()