Lines Matching refs:VCN
298 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) in vcn_v2_0_hw_fini()
514 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
521 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
523 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
544 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
546 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
567 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
570 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
595 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
597 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
608 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
676 SOC15_WAIT_ON_RREG(VCN, 0, in jpeg_v2_0_start()
690 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in jpeg_v2_0_start()
694 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp); in jpeg_v2_0_start()
696 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in jpeg_v2_0_start()
702 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp); in jpeg_v2_0_start()
709 WREG32_P(SOC15_REG_OFFSET(VCN, 0, mmJPEG_SYS_INT_EN), in jpeg_v2_0_start()
746 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in jpeg_v2_0_stop()
750 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, tmp); in jpeg_v2_0_stop()
753 tmp = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in jpeg_v2_0_stop()
759 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, tmp); in jpeg_v2_0_stop()
770 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, in jpeg_v2_0_stop()
795 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
802 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
804 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
825 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
827 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
838 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
858 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_disable_static_power_gating()
859 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, in vcn_v2_0_disable_static_power_gating()
872 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_disable_static_power_gating()
873 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF, ret); in vcn_v2_0_disable_static_power_gating()
879 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_v2_0_disable_static_power_gating()
885 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_disable_static_power_gating()
895 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_v2_0_enable_static_power_gating()
898 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_enable_static_power_gating()
912 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_v2_0_enable_static_power_gating()
924 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret); in vcn_v2_0_enable_static_power_gating()
1100 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); in vcn_v2_0_start()
1132 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); in vcn_v2_0_start()
1135 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); in vcn_v2_0_start()
1276 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r); in vcn_v2_0_stop()
1284 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r); in vcn_v2_0_stop()
1289 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); in vcn_v2_0_stop()
1291 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); in vcn_v2_0_stop()
1295 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp, r); in vcn_v2_0_stop()
1319 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); in vcn_v2_0_stop()
1397 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_0_is_idle()
1405 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_0_wait_for_idle()