1852 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_insert_start()
1856 	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in vcn_v2_0_jpeg_ring_insert_start()
1870 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_insert_end()
1874 	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in vcn_v2_0_jpeg_ring_insert_end()
1892 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_fence()
1896 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_fence()
1900 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_fence()
1904 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_fence()
1908 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_fence()
1912 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_fence()
1916 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_fence()
1920 	amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in vcn_v2_0_jpeg_ring_emit_fence()
1924 	amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));  in vcn_v2_0_jpeg_ring_emit_fence()
1943 	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_ib()
1947 	amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_ib()
1951 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_ib()
1955 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_ib()
1959 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_ib()
1963 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_ib()
1967 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_ib()
1971 	amdgpu_ring_write(ring,	PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));  in vcn_v2_0_jpeg_ring_emit_ib()
1974 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_ib()
1978 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_ib()
1982 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_ib()
1992 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_reg_wait()
1996 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_reg_wait()
2000 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_reg_wait()
2005 			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));  in vcn_v2_0_jpeg_ring_emit_reg_wait()
2008 		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in vcn_v2_0_jpeg_ring_emit_reg_wait()
2033 	amdgpu_ring_write(ring,	PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,  in vcn_v2_0_jpeg_ring_emit_wreg()
2038 			PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));  in vcn_v2_0_jpeg_ring_emit_wreg()
2041 		amdgpu_ring_write(ring,	PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,  in vcn_v2_0_jpeg_ring_emit_wreg()
2054 		amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));  in vcn_v2_0_jpeg_ring_nop()