Lines Matching refs:vcn
66 adev->vcn.num_vcn_inst = 1; in vcn_v1_0_early_init()
67 adev->vcn.num_enc_rings = 2; in vcn_v1_0_early_init()
92 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq); in vcn_v1_0_sw_init()
97 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v1_0_sw_init()
99 &adev->vcn.inst->irq); in vcn_v1_0_sw_init()
105 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.inst->irq); in vcn_v1_0_sw_init()
115 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; in vcn_v1_0_sw_init()
117 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; in vcn_v1_0_sw_init()
127 ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_sw_init()
129 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); in vcn_v1_0_sw_init()
133 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 = in vcn_v1_0_sw_init()
135 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 = in vcn_v1_0_sw_init()
137 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 = in vcn_v1_0_sw_init()
139 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd = in vcn_v1_0_sw_init()
141 adev->vcn.internal.nop = adev->vcn.inst->external.nop = in vcn_v1_0_sw_init()
144 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v1_0_sw_init()
145 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v1_0_sw_init()
147 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); in vcn_v1_0_sw_init()
152 ring = &adev->vcn.inst->ring_jpeg; in vcn_v1_0_sw_init()
154 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); in vcn_v1_0_sw_init()
158 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode; in vcn_v1_0_sw_init()
159 adev->vcn.internal.jpeg_pitch = adev->vcn.inst->external.jpeg_pitch = in vcn_v1_0_sw_init()
196 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_hw_init()
203 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in vcn_v1_0_hw_init()
204 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v1_0_hw_init()
211 ring = &adev->vcn.inst->ring_jpeg; in vcn_v1_0_hw_init()
234 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_hw_fini()
296 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v1_0_mc_resume_spg_mode()
309 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
311 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
321 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v1_0_mc_resume_spg_mode()
323 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v1_0_mc_resume_spg_mode()
329 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
331 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
363 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); in vcn_v1_0_mc_resume_dpg_mode()
379 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
381 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
391 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
393 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
401 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
404 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
784 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_start_spg_mode()
937 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v1_0_start_spg_mode()
944 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v1_0_start_spg_mode()
951 ring = &adev->vcn.inst->ring_jpeg; in vcn_v1_0_start_spg_mode()
973 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_start_dpg_mode()
1111 ring = &adev->vcn.inst->ring_jpeg; in vcn_v1_0_start_dpg_mode()
1235 if (adev->vcn.pause_state.fw_based != new_state->fw_based) { in vcn_v1_0_pause_dpg_mode()
1237 adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1260 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v1_0_pause_dpg_mode()
1267 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v1_0_pause_dpg_mode()
1274 ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_pause_dpg_mode()
1286 adev->vcn.pause_state.fw_based = new_state->fw_based; in vcn_v1_0_pause_dpg_mode()
1290 if (adev->vcn.pause_state.jpeg != new_state->jpeg) { in vcn_v1_0_pause_dpg_mode()
1292 adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1320 ring = &adev->vcn.inst->ring_jpeg; in vcn_v1_0_pause_dpg_mode()
1334 ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_pause_dpg_mode()
1346 adev->vcn.pause_state.jpeg = new_state->jpeg; in vcn_v1_0_pause_dpg_mode()
1601 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v1_0_enc_ring_get_rptr()
1618 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v1_0_enc_ring_get_wptr()
1635 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v1_0_enc_ring_set_wptr()
2119 amdgpu_fence_process(&adev->vcn.inst->ring_dec); in vcn_v1_0_process_interrupt()
2122 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); in vcn_v1_0_process_interrupt()
2125 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); in vcn_v1_0_process_interrupt()
2128 amdgpu_fence_process(&adev->vcn.inst->ring_jpeg); in vcn_v1_0_process_interrupt()
2165 if(state == adev->vcn.cur_state) in vcn_v1_0_set_powergating_state()
2174 adev->vcn.cur_state = state; in vcn_v1_0_set_powergating_state()
2300 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; in vcn_v1_0_set_dec_ring_funcs()
2308 for (i = 0; i < adev->vcn.num_enc_rings; ++i) in vcn_v1_0_set_enc_ring_funcs()
2309 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; in vcn_v1_0_set_enc_ring_funcs()
2316 adev->vcn.inst->ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs; in vcn_v1_0_set_jpeg_ring_funcs()
2327 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; in vcn_v1_0_set_irq_funcs()
2328 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs; in vcn_v1_0_set_irq_funcs()