Lines Matching refs:ring
50 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr);
86 struct amdgpu_ring *ring; in vcn_v1_0_sw_init() local
127 ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_sw_init()
128 sprintf(ring->name, "vcn_dec"); in vcn_v1_0_sw_init()
129 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); in vcn_v1_0_sw_init()
145 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v1_0_sw_init()
146 sprintf(ring->name, "vcn_enc%d", i); in vcn_v1_0_sw_init()
147 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); in vcn_v1_0_sw_init()
152 ring = &adev->vcn.inst->ring_jpeg; in vcn_v1_0_sw_init()
153 sprintf(ring->name, "vcn_jpeg"); in vcn_v1_0_sw_init()
154 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); in vcn_v1_0_sw_init()
196 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_hw_init() local
199 r = amdgpu_ring_test_helper(ring); in vcn_v1_0_hw_init()
204 ring = &adev->vcn.inst->ring_enc[i]; in vcn_v1_0_hw_init()
205 ring->sched.ready = true; in vcn_v1_0_hw_init()
206 r = amdgpu_ring_test_helper(ring); in vcn_v1_0_hw_init()
211 ring = &adev->vcn.inst->ring_jpeg; in vcn_v1_0_hw_init()
212 r = amdgpu_ring_test_helper(ring); in vcn_v1_0_hw_init()
234 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_hw_fini() local
240 ring->sched.ready = false; in vcn_v1_0_hw_fini()
784 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_start_spg_mode() local
904 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start_spg_mode()
917 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start_spg_mode()
921 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
923 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
930 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v1_0_start_spg_mode()
932 lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
937 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v1_0_start_spg_mode()
938 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
939 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
940 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v1_0_start_spg_mode()
941 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
942 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v1_0_start_spg_mode()
944 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v1_0_start_spg_mode()
945 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
946 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
947 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v1_0_start_spg_mode()
948 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
949 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v1_0_start_spg_mode()
951 ring = &adev->vcn.inst->ring_jpeg; in vcn_v1_0_start_spg_mode()
955 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
956 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
962 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); in vcn_v1_0_start_spg_mode()
965 vcn_v1_0_jpeg_ring_set_patch_ring(ring, in vcn_v1_0_start_spg_mode()
966 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission)); in vcn_v1_0_start_spg_mode()
973 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_start_dpg_mode() local
1077 rb_bufsz = order_base_2(ring->ring_size); in vcn_v1_0_start_dpg_mode()
1090 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start_dpg_mode()
1094 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_dpg_mode()
1096 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_dpg_mode()
1103 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); in vcn_v1_0_start_dpg_mode()
1105 lower_32_bits(ring->wptr)); in vcn_v1_0_start_dpg_mode()
1111 ring = &adev->vcn.inst->ring_jpeg; in vcn_v1_0_start_dpg_mode()
1112 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); in vcn_v1_0_start_dpg_mode()
1115 vcn_v1_0_jpeg_ring_set_patch_ring(ring, in vcn_v1_0_start_dpg_mode()
1116 (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission)); in vcn_v1_0_start_dpg_mode()
1232 struct amdgpu_ring *ring; in vcn_v1_0_pause_dpg_mode() local
1260 ring = &adev->vcn.inst->ring_enc[0]; in vcn_v1_0_pause_dpg_mode()
1261 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v1_0_pause_dpg_mode()
1262 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
1263 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v1_0_pause_dpg_mode()
1264 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1265 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1267 ring = &adev->vcn.inst->ring_enc[1]; in vcn_v1_0_pause_dpg_mode()
1268 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v1_0_pause_dpg_mode()
1269 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
1270 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v1_0_pause_dpg_mode()
1271 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1272 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1274 ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_pause_dpg_mode()
1320 ring = &adev->vcn.inst->ring_jpeg; in vcn_v1_0_pause_dpg_mode()
1326 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
1328 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
1329 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); in vcn_v1_0_pause_dpg_mode()
1330 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); in vcn_v1_0_pause_dpg_mode()
1334 ring = &adev->vcn.inst->ring_dec; in vcn_v1_0_pause_dpg_mode()
1395 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) in vcn_v1_0_dec_ring_get_rptr() argument
1397 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_dec_ring_get_rptr()
1409 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) in vcn_v1_0_dec_ring_get_wptr() argument
1411 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_dec_ring_get_wptr()
1423 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) in vcn_v1_0_dec_ring_set_wptr() argument
1425 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_dec_ring_set_wptr()
1429 lower_32_bits(ring->wptr) | 0x80000000); in vcn_v1_0_dec_ring_set_wptr()
1431 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_dec_ring_set_wptr()
1441 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) in vcn_v1_0_dec_ring_insert_start() argument
1443 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_dec_ring_insert_start()
1445 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1447 amdgpu_ring_write(ring, 0); in vcn_v1_0_dec_ring_insert_start()
1448 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_start()
1450 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); in vcn_v1_0_dec_ring_insert_start()
1460 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) in vcn_v1_0_dec_ring_insert_end() argument
1462 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_dec_ring_insert_end()
1464 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_insert_end()
1466 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); in vcn_v1_0_dec_ring_insert_end()
1477 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, in vcn_v1_0_dec_ring_emit_fence() argument
1480 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_dec_ring_emit_fence()
1484 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1486 amdgpu_ring_write(ring, seq); in vcn_v1_0_dec_ring_emit_fence()
1487 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1489 amdgpu_ring_write(ring, addr & 0xffffffff); in vcn_v1_0_dec_ring_emit_fence()
1490 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1492 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); in vcn_v1_0_dec_ring_emit_fence()
1493 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1495 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); in vcn_v1_0_dec_ring_emit_fence()
1497 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1499 amdgpu_ring_write(ring, 0); in vcn_v1_0_dec_ring_emit_fence()
1500 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1502 amdgpu_ring_write(ring, 0); in vcn_v1_0_dec_ring_emit_fence()
1503 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_fence()
1505 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); in vcn_v1_0_dec_ring_emit_fence()
1516 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, in vcn_v1_0_dec_ring_emit_ib() argument
1521 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_dec_ring_emit_ib()
1524 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_ib()
1526 amdgpu_ring_write(ring, vmid); in vcn_v1_0_dec_ring_emit_ib()
1528 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_ib()
1530 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_v1_0_dec_ring_emit_ib()
1531 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_ib()
1533 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_v1_0_dec_ring_emit_ib()
1534 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_ib()
1536 amdgpu_ring_write(ring, ib->length_dw); in vcn_v1_0_dec_ring_emit_ib()
1539 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, in vcn_v1_0_dec_ring_emit_reg_wait() argument
1543 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_dec_ring_emit_reg_wait()
1545 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_reg_wait()
1547 amdgpu_ring_write(ring, reg << 2); in vcn_v1_0_dec_ring_emit_reg_wait()
1548 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_reg_wait()
1550 amdgpu_ring_write(ring, val); in vcn_v1_0_dec_ring_emit_reg_wait()
1551 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_reg_wait()
1553 amdgpu_ring_write(ring, mask); in vcn_v1_0_dec_ring_emit_reg_wait()
1554 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_reg_wait()
1556 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); in vcn_v1_0_dec_ring_emit_reg_wait()
1559 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, in vcn_v1_0_dec_ring_emit_vm_flush() argument
1562 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; in vcn_v1_0_dec_ring_emit_vm_flush()
1565 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in vcn_v1_0_dec_ring_emit_vm_flush()
1571 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); in vcn_v1_0_dec_ring_emit_vm_flush()
1574 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, in vcn_v1_0_dec_ring_emit_wreg() argument
1577 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_dec_ring_emit_wreg()
1579 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_wreg()
1581 amdgpu_ring_write(ring, reg << 2); in vcn_v1_0_dec_ring_emit_wreg()
1582 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_wreg()
1584 amdgpu_ring_write(ring, val); in vcn_v1_0_dec_ring_emit_wreg()
1585 amdgpu_ring_write(ring, in vcn_v1_0_dec_ring_emit_wreg()
1587 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); in vcn_v1_0_dec_ring_emit_wreg()
1597 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) in vcn_v1_0_enc_ring_get_rptr() argument
1599 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_enc_ring_get_rptr()
1601 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v1_0_enc_ring_get_rptr()
1614 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) in vcn_v1_0_enc_ring_get_wptr() argument
1616 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_enc_ring_get_wptr()
1618 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v1_0_enc_ring_get_wptr()
1631 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) in vcn_v1_0_enc_ring_set_wptr() argument
1633 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_enc_ring_set_wptr()
1635 if (ring == &adev->vcn.inst->ring_enc[0]) in vcn_v1_0_enc_ring_set_wptr()
1637 lower_32_bits(ring->wptr)); in vcn_v1_0_enc_ring_set_wptr()
1640 lower_32_bits(ring->wptr)); in vcn_v1_0_enc_ring_set_wptr()
1651 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, in vcn_v1_0_enc_ring_emit_fence() argument
1656 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); in vcn_v1_0_enc_ring_emit_fence()
1657 amdgpu_ring_write(ring, addr); in vcn_v1_0_enc_ring_emit_fence()
1658 amdgpu_ring_write(ring, upper_32_bits(addr)); in vcn_v1_0_enc_ring_emit_fence()
1659 amdgpu_ring_write(ring, seq); in vcn_v1_0_enc_ring_emit_fence()
1660 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); in vcn_v1_0_enc_ring_emit_fence()
1663 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) in vcn_v1_0_enc_ring_insert_end() argument
1665 amdgpu_ring_write(ring, VCN_ENC_CMD_END); in vcn_v1_0_enc_ring_insert_end()
1676 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, in vcn_v1_0_enc_ring_emit_ib() argument
1683 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); in vcn_v1_0_enc_ring_emit_ib()
1684 amdgpu_ring_write(ring, vmid); in vcn_v1_0_enc_ring_emit_ib()
1685 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_v1_0_enc_ring_emit_ib()
1686 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_v1_0_enc_ring_emit_ib()
1687 amdgpu_ring_write(ring, ib->length_dw); in vcn_v1_0_enc_ring_emit_ib()
1690 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, in vcn_v1_0_enc_ring_emit_reg_wait() argument
1694 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); in vcn_v1_0_enc_ring_emit_reg_wait()
1695 amdgpu_ring_write(ring, reg << 2); in vcn_v1_0_enc_ring_emit_reg_wait()
1696 amdgpu_ring_write(ring, mask); in vcn_v1_0_enc_ring_emit_reg_wait()
1697 amdgpu_ring_write(ring, val); in vcn_v1_0_enc_ring_emit_reg_wait()
1700 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, in vcn_v1_0_enc_ring_emit_vm_flush() argument
1703 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; in vcn_v1_0_enc_ring_emit_vm_flush()
1705 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in vcn_v1_0_enc_ring_emit_vm_flush()
1708 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, in vcn_v1_0_enc_ring_emit_vm_flush()
1712 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, in vcn_v1_0_enc_ring_emit_wreg() argument
1715 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); in vcn_v1_0_enc_ring_emit_wreg()
1716 amdgpu_ring_write(ring, reg << 2); in vcn_v1_0_enc_ring_emit_wreg()
1717 amdgpu_ring_write(ring, val); in vcn_v1_0_enc_ring_emit_wreg()
1728 static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring) in vcn_v1_0_jpeg_ring_get_rptr() argument
1730 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_jpeg_ring_get_rptr()
1742 static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring) in vcn_v1_0_jpeg_ring_get_wptr() argument
1744 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_jpeg_ring_get_wptr()
1756 static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring) in vcn_v1_0_jpeg_ring_set_wptr() argument
1758 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_jpeg_ring_set_wptr()
1760 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_jpeg_ring_set_wptr()
1770 static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring) in vcn_v1_0_jpeg_ring_insert_start() argument
1772 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_jpeg_ring_insert_start()
1774 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_insert_start()
1776 amdgpu_ring_write(ring, 0x68e04); in vcn_v1_0_jpeg_ring_insert_start()
1778 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in vcn_v1_0_jpeg_ring_insert_start()
1779 amdgpu_ring_write(ring, 0x80010000); in vcn_v1_0_jpeg_ring_insert_start()
1789 static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring) in vcn_v1_0_jpeg_ring_insert_end() argument
1791 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_jpeg_ring_insert_end()
1793 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_insert_end()
1795 amdgpu_ring_write(ring, 0x68e04); in vcn_v1_0_jpeg_ring_insert_end()
1797 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0)); in vcn_v1_0_jpeg_ring_insert_end()
1798 amdgpu_ring_write(ring, 0x00010000); in vcn_v1_0_jpeg_ring_insert_end()
1809 static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, in vcn_v1_0_jpeg_ring_emit_fence() argument
1812 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_jpeg_ring_emit_fence()
1816 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_fence()
1818 amdgpu_ring_write(ring, seq); in vcn_v1_0_jpeg_ring_emit_fence()
1820 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_fence()
1822 amdgpu_ring_write(ring, seq); in vcn_v1_0_jpeg_ring_emit_fence()
1824 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_fence()
1826 amdgpu_ring_write(ring, lower_32_bits(addr)); in vcn_v1_0_jpeg_ring_emit_fence()
1828 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_fence()
1830 amdgpu_ring_write(ring, upper_32_bits(addr)); in vcn_v1_0_jpeg_ring_emit_fence()
1832 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_fence()
1834 amdgpu_ring_write(ring, 0x8); in vcn_v1_0_jpeg_ring_emit_fence()
1836 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_fence()
1838 amdgpu_ring_write(ring, 0); in vcn_v1_0_jpeg_ring_emit_fence()
1840 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_fence()
1842 amdgpu_ring_write(ring, 0x01400200); in vcn_v1_0_jpeg_ring_emit_fence()
1844 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_fence()
1846 amdgpu_ring_write(ring, seq); in vcn_v1_0_jpeg_ring_emit_fence()
1848 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_fence()
1850 amdgpu_ring_write(ring, lower_32_bits(addr)); in vcn_v1_0_jpeg_ring_emit_fence()
1852 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_fence()
1854 amdgpu_ring_write(ring, upper_32_bits(addr)); in vcn_v1_0_jpeg_ring_emit_fence()
1856 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_fence()
1858 amdgpu_ring_write(ring, 0xffffffff); in vcn_v1_0_jpeg_ring_emit_fence()
1860 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_fence()
1862 amdgpu_ring_write(ring, 0x3fbc); in vcn_v1_0_jpeg_ring_emit_fence()
1864 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_fence()
1866 amdgpu_ring_write(ring, 0x1); in vcn_v1_0_jpeg_ring_emit_fence()
1869 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); in vcn_v1_0_jpeg_ring_emit_fence()
1870 amdgpu_ring_write(ring, 0); in vcn_v1_0_jpeg_ring_emit_fence()
1881 static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, in vcn_v1_0_jpeg_ring_emit_ib() argument
1886 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_jpeg_ring_emit_ib()
1889 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_ib()
1891 amdgpu_ring_write(ring, (vmid | (vmid << 4))); in vcn_v1_0_jpeg_ring_emit_ib()
1893 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_ib()
1895 amdgpu_ring_write(ring, (vmid | (vmid << 4))); in vcn_v1_0_jpeg_ring_emit_ib()
1897 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_ib()
1899 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vcn_v1_0_jpeg_ring_emit_ib()
1901 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_ib()
1903 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vcn_v1_0_jpeg_ring_emit_ib()
1905 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_ib()
1907 amdgpu_ring_write(ring, ib->length_dw); in vcn_v1_0_jpeg_ring_emit_ib()
1909 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_ib()
1911 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); in vcn_v1_0_jpeg_ring_emit_ib()
1913 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_ib()
1915 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_jpeg_ring_emit_ib()
1917 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_ib()
1919 amdgpu_ring_write(ring, 0); in vcn_v1_0_jpeg_ring_emit_ib()
1921 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_ib()
1923 amdgpu_ring_write(ring, 0x01400200); in vcn_v1_0_jpeg_ring_emit_ib()
1925 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_ib()
1927 amdgpu_ring_write(ring, 0x2); in vcn_v1_0_jpeg_ring_emit_ib()
1929 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_ib()
1931 amdgpu_ring_write(ring, 0x2); in vcn_v1_0_jpeg_ring_emit_ib()
1934 static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, in vcn_v1_0_jpeg_ring_emit_reg_wait() argument
1938 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_jpeg_ring_emit_reg_wait()
1941 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_reg_wait()
1943 amdgpu_ring_write(ring, 0x01400200); in vcn_v1_0_jpeg_ring_emit_reg_wait()
1945 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_reg_wait()
1947 amdgpu_ring_write(ring, val); in vcn_v1_0_jpeg_ring_emit_reg_wait()
1949 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_reg_wait()
1953 amdgpu_ring_write(ring, 0); in vcn_v1_0_jpeg_ring_emit_reg_wait()
1954 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_reg_wait()
1957 amdgpu_ring_write(ring, reg_offset); in vcn_v1_0_jpeg_ring_emit_reg_wait()
1958 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_reg_wait()
1961 amdgpu_ring_write(ring, mask); in vcn_v1_0_jpeg_ring_emit_reg_wait()
1964 static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring, in vcn_v1_0_jpeg_ring_emit_vm_flush() argument
1967 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; in vcn_v1_0_jpeg_ring_emit_vm_flush()
1970 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); in vcn_v1_0_jpeg_ring_emit_vm_flush()
1976 vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask); in vcn_v1_0_jpeg_ring_emit_vm_flush()
1979 static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, in vcn_v1_0_jpeg_ring_emit_wreg() argument
1982 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_jpeg_ring_emit_wreg()
1985 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_wreg()
1989 amdgpu_ring_write(ring, 0); in vcn_v1_0_jpeg_ring_emit_wreg()
1990 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_wreg()
1993 amdgpu_ring_write(ring, reg_offset); in vcn_v1_0_jpeg_ring_emit_wreg()
1994 amdgpu_ring_write(ring, in vcn_v1_0_jpeg_ring_emit_wreg()
1997 amdgpu_ring_write(ring, val); in vcn_v1_0_jpeg_ring_emit_wreg()
2000 static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count) in vcn_v1_0_jpeg_ring_nop() argument
2004 WARN_ON(ring->wptr % 2 || count % 2); in vcn_v1_0_jpeg_ring_nop()
2007 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); in vcn_v1_0_jpeg_ring_nop()
2008 amdgpu_ring_write(ring, 0); in vcn_v1_0_jpeg_ring_nop()
2012 static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_off… in vcn_v1_0_jpeg_ring_patch_wreg() argument
2014 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_jpeg_ring_patch_wreg()
2015 …ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKE… in vcn_v1_0_jpeg_ring_patch_wreg()
2018 ring->ring[(*ptr)++] = 0; in vcn_v1_0_jpeg_ring_patch_wreg()
2019 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0); in vcn_v1_0_jpeg_ring_patch_wreg()
2021 ring->ring[(*ptr)++] = reg_offset; in vcn_v1_0_jpeg_ring_patch_wreg()
2022 ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0); in vcn_v1_0_jpeg_ring_patch_wreg()
2024 ring->ring[(*ptr)++] = val; in vcn_v1_0_jpeg_ring_patch_wreg()
2027 static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr) in vcn_v1_0_jpeg_ring_set_patch_ring() argument
2029 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_jpeg_ring_set_patch_ring()
2036 val = lower_32_bits(ring->gpu_addr); in vcn_v1_0_jpeg_ring_set_patch_ring()
2037 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); in vcn_v1_0_jpeg_ring_set_patch_ring()
2042 val = upper_32_bits(ring->gpu_addr); in vcn_v1_0_jpeg_ring_set_patch_ring()
2043 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); in vcn_v1_0_jpeg_ring_set_patch_ring()
2047 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2); in vcn_v1_0_jpeg_ring_set_patch_ring()
2048 ring->ring[ptr++] = 0; in vcn_v1_0_jpeg_ring_set_patch_ring()
2055 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); in vcn_v1_0_jpeg_ring_set_patch_ring()
2061 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); in vcn_v1_0_jpeg_ring_set_patch_ring()
2069 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_T… in vcn_v1_0_jpeg_ring_set_patch_ring()
2070 ring->ring[ptr++] = 0x01400200; in vcn_v1_0_jpeg_ring_set_patch_ring()
2071 ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0); in vcn_v1_0_jpeg_ring_set_patch_ring()
2072 ring->ring[ptr++] = val; in vcn_v1_0_jpeg_ring_set_patch_ring()
2073 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_… in vcn_v1_0_jpeg_ring_set_patch_ring()
2076 ring->ring[ptr++] = 0; in vcn_v1_0_jpeg_ring_set_patch_ring()
2077 ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3); in vcn_v1_0_jpeg_ring_set_patch_ring()
2079 ring->ring[ptr++] = reg_offset; in vcn_v1_0_jpeg_ring_set_patch_ring()
2080 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3); in vcn_v1_0_jpeg_ring_set_patch_ring()
2082 ring->ring[ptr++] = mask; in vcn_v1_0_jpeg_ring_set_patch_ring()
2086 ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6); in vcn_v1_0_jpeg_ring_set_patch_ring()
2087 ring->ring[ptr++] = 0; in vcn_v1_0_jpeg_ring_set_patch_ring()
2094 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); in vcn_v1_0_jpeg_ring_set_patch_ring()
2100 vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val); in vcn_v1_0_jpeg_ring_set_patch_ring()
2139 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) in vcn_v1_0_dec_ring_insert_nop() argument
2141 struct amdgpu_device *adev = ring->adev; in vcn_v1_0_dec_ring_insert_nop()
2144 WARN_ON(ring->wptr % 2 || count % 2); in vcn_v1_0_dec_ring_insert_nop()
2147 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); in vcn_v1_0_dec_ring_insert_nop()
2148 amdgpu_ring_write(ring, 0); in vcn_v1_0_dec_ring_insert_nop()