Lines Matching refs:VCN

237 		RREG32_SOC15(VCN, 0, mmUVD_STATUS))  in vcn_v1_0_hw_fini()
446 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
455 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
457 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_disable_clock_gating()
459 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
462 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
470 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
472 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
493 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
495 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
516 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
519 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
544 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
546 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
557 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
573 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
580 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
582 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); in vcn_v1_0_enable_clock_gating()
584 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); in vcn_v1_0_enable_clock_gating()
587 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
594 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
596 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
617 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
619 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
630 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
705 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_1_0_disable_static_power_gating()
706 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret); in vcn_1_0_disable_static_power_gating()
719 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_1_0_disable_static_power_gating()
720 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF, ret); in vcn_1_0_disable_static_power_gating()
725 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_1_0_disable_static_power_gating()
730 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_1_0_disable_static_power_gating()
740 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_1_0_enable_static_power_gating()
743 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_1_0_enable_static_power_gating()
758 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); in vcn_1_0_enable_static_power_gating()
771 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret); in vcn_1_0_enable_static_power_gating()
1356 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle()
1364 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v1_0_wait_for_idle()