Lines Matching refs:vce
178 WDOORBELL32(adev->vce.ring[0].doorbell_index, 0); in vce_v4_0_mmsch_start()
179 adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0; in vce_v4_0_mmsch_start()
180 adev->vce.ring[0].wptr = 0; in vce_v4_0_mmsch_start()
181 adev->vce.ring[0].wptr_old = 0; in vce_v4_0_mmsch_start()
232 ring = &adev->vce.ring[0]; in vce_v4_0_sriov_start()
262 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
265 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
272 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
275 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
278 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
281 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
340 ring = &adev->vce.ring[0]; in vce_v4_0_start()
348 ring = &adev->vce.ring[1]; in vce_v4_0_start()
356 ring = &adev->vce.ring[2]; in vce_v4_0_start()
414 adev->vce.num_rings = 1; in vce_v4_0_early_init()
416 adev->vce.num_rings = 3; in vce_v4_0_early_init()
432 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCE0, 167, &adev->vce.irq); in vce_v4_0_sw_init()
446 unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo); in vce_v4_0_sw_init()
448 adev->vce.saved_bo = kvmalloc(size, GFP_KERNEL); in vce_v4_0_sw_init()
449 if (!adev->vce.saved_bo) in vce_v4_0_sw_init()
452 hdr = (const struct common_firmware_header *)adev->vce.fw->data; in vce_v4_0_sw_init()
454 adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].fw = adev->vce.fw; in vce_v4_0_sw_init()
464 for (i = 0; i < adev->vce.num_rings; i++) { in vce_v4_0_sw_init()
465 ring = &adev->vce.ring[i]; in vce_v4_0_sw_init()
479 r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0); in vce_v4_0_sw_init()
505 kvfree(adev->vce.saved_bo); in vce_v4_0_sw_fini()
506 adev->vce.saved_bo = NULL; in vce_v4_0_sw_fini()
528 for (i = 0; i < adev->vce.num_rings; i++) { in vce_v4_0_hw_init()
529 r = amdgpu_ring_test_helper(&adev->vce.ring[i]); in vce_v4_0_hw_init()
552 for (i = 0; i < adev->vce.num_rings; i++) in vce_v4_0_hw_fini()
553 adev->vce.ring[i].sched.ready = false; in vce_v4_0_hw_fini()
563 if (adev->vce.vcpu_bo == NULL) in vce_v4_0_suspend()
567 unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo); in vce_v4_0_suspend()
568 void *ptr = adev->vce.cpu_addr; in vce_v4_0_suspend()
570 memcpy_fromio(adev->vce.saved_bo, ptr, size); in vce_v4_0_suspend()
585 if (adev->vce.vcpu_bo == NULL) in vce_v4_0_resume()
589 unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo); in vce_v4_0_resume()
590 void *ptr = adev->vce.cpu_addr; in vce_v4_0_resume()
592 memcpy_toio(ptr, adev->vce.saved_bo, size); in vce_v4_0_resume()
630 (adev->vce.gpu_addr >> 8)); in vce_v4_0_mc_resume()
632 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_mc_resume()
639 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), (adev->vce.gpu_addr >> 8)); in vce_v4_0_mc_resume()
640 …WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), (adev->vce.gpu_addr >> 40) & 0xf… in vce_v4_0_mc_resume()
646 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), (adev->vce.gpu_addr >> 8)); in vce_v4_0_mc_resume()
647 …WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), (adev->vce.gpu_addr >> 40) & 0xf… in vce_v4_0_mc_resume()
672 mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE0) ? 0 : SRBM_STATUS2__VCE0_BUSY_MASK;
673 mask |= (adev->vce.harvest_config & AMDGPU_VCE_HARVEST_VCE1) ? 0 : SRBM_STATUS2__VCE1_BUSY_MASK;
729 adev->vce.srbm_soft_reset = srbm_soft_reset;
732 adev->vce.srbm_soft_reset = 0;
742 if (!adev->vce.srbm_soft_reset)
744 srbm_soft_reset = adev->vce.srbm_soft_reset;
772 if (!adev->vce.srbm_soft_reset)
785 if (!adev->vce.srbm_soft_reset)
904 if (adev->vce.harvest_config & (1 << i))
1036 amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]); in vce_v4_0_process_interrupt()
1104 for (i = 0; i < adev->vce.num_rings; i++) { in vce_v4_0_set_ring_funcs()
1105 adev->vce.ring[i].funcs = &vce_v4_0_ring_vm_funcs; in vce_v4_0_set_ring_funcs()
1106 adev->vce.ring[i].me = i; in vce_v4_0_set_ring_funcs()
1118 adev->vce.irq.num_types = 1; in vce_v4_0_set_irq_funcs()
1119 adev->vce.irq.funcs = &vce_v4_0_irq_funcs; in vce_v4_0_set_irq_funcs()