Lines Matching refs:me
75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); in uvd_v7_0_ring_get_rptr()
89 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_rptr()
90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); in uvd_v7_0_enc_ring_get_rptr()
92 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); in uvd_v7_0_enc_ring_get_rptr()
106 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); in uvd_v7_0_ring_get_wptr()
123 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_wptr()
124 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); in uvd_v7_0_enc_ring_get_wptr()
126 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); in uvd_v7_0_enc_ring_get_wptr()
140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_ring_set_wptr()
161 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_set_wptr()
162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, in uvd_v7_0_enc_ring_set_wptr()
165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, in uvd_v7_0_enc_ring_set_wptr()
452 sprintf(ring->name, "uvd_%d", ring->me); in uvd_v7_0_sw_init()
460 sprintf(ring->name, "uvd_enc_%d.%d", ring->me, i); in uvd_v7_0_sw_init()
1163 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); in uvd_v7_0_ring_emit_fence()
1166 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_fence()
1169 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_fence()
1172 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_fence()
1176 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_fence()
1179 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_fence()
1182 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_fence()
1231 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v7_0_ring_test_ring()
1237 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); in uvd_v7_0_ring_test_ring()
1241 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); in uvd_v7_0_ring_test_ring()
1268 if (!ring->me) in uvd_v7_0_ring_patch_cs_in_place()
1299 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); in uvd_v7_0_ring_emit_ib()
1303 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); in uvd_v7_0_ring_emit_ib()
1306 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); in uvd_v7_0_ring_emit_ib()
1309 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0)); in uvd_v7_0_ring_emit_ib()
1341 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_wreg()
1344 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_wreg()
1347 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_wreg()
1357 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_reg_wait()
1360 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_reg_wait()
1363 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); in uvd_v7_0_ring_emit_reg_wait()
1366 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_reg_wait()
1393 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); in uvd_v7_0_ring_insert_nop()
1462 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
1468 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1471 adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1480 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1492 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1494 srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1522 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1585 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1586 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1587 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1631 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
1632 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1633 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1634 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
1641 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1642 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1674 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
1675 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1734 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1845 adev->uvd.inst[i].ring.me = i; in uvd_v7_0_set_ring_funcs()
1859 adev->uvd.inst[j].ring_enc[i].me = j; in uvd_v7_0_set_enc_ring_funcs()