550 			tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
555 			tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
560 			tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
566 			amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
570 			amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,  in uvd_v7_0_hw_init()
1163 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));  in uvd_v7_0_ring_emit_fence()
1166 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_fence()
1169 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_fence()
1172 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_fence()
1176 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_fence()
1179 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_fence()
1182 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_fence()
1237 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));  in uvd_v7_0_ring_test_ring()
1299 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));  in uvd_v7_0_ring_emit_ib()
1303 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));  in uvd_v7_0_ring_emit_ib()
1306 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));  in uvd_v7_0_ring_emit_ib()
1309 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));  in uvd_v7_0_ring_emit_ib()
1341 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_wreg()
1344 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_wreg()
1347 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_wreg()
1357 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_reg_wait()
1360 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_reg_wait()
1363 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));  in uvd_v7_0_ring_emit_reg_wait()
1366 		PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_reg_wait()
1393 		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));  in uvd_v7_0_ring_insert_nop()