487 	tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);  in uvd_v6_0_hw_init()
491 	tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);  in uvd_v6_0_hw_init()
495 	tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);  in uvd_v6_0_hw_init()
500 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));  in uvd_v6_0_hw_init()
503 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));  in uvd_v6_0_hw_init()
901 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));  in uvd_v6_0_ring_emit_fence()
903 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v6_0_ring_emit_fence()
905 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v6_0_ring_emit_fence()
907 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v6_0_ring_emit_fence()
910 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v6_0_ring_emit_fence()
912 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v6_0_ring_emit_fence()
914 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v6_0_ring_emit_fence()
967 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));  in uvd_v6_0_ring_test_ring()
998 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));  in uvd_v6_0_ring_emit_ib()
1001 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));  in uvd_v6_0_ring_emit_ib()
1003 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));  in uvd_v6_0_ring_emit_ib()
1005 	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));  in uvd_v6_0_ring_emit_ib()
1034 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v6_0_ring_emit_wreg()
1036 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v6_0_ring_emit_wreg()
1038 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v6_0_ring_emit_wreg()
1047 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v6_0_ring_emit_vm_flush()
1049 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v6_0_ring_emit_vm_flush()
1051 	amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));  in uvd_v6_0_ring_emit_vm_flush()
1053 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v6_0_ring_emit_vm_flush()
1062 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v6_0_ring_emit_pipeline_sync()
1064 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v6_0_ring_emit_pipeline_sync()
1066 	amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));  in uvd_v6_0_ring_emit_pipeline_sync()
1068 	amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));  in uvd_v6_0_ring_emit_pipeline_sync()
1070 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v6_0_ring_emit_pipeline_sync()
1081 		amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));  in uvd_v6_0_ring_insert_nop()