172 	tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);  in uvd_v5_0_hw_init()
176 	tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);  in uvd_v5_0_hw_init()
180 	tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);  in uvd_v5_0_hw_init()
185 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));  in uvd_v5_0_hw_init()
188 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));  in uvd_v5_0_hw_init()
468 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));  in uvd_v5_0_ring_emit_fence()
470 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v5_0_ring_emit_fence()
472 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v5_0_ring_emit_fence()
474 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v5_0_ring_emit_fence()
477 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v5_0_ring_emit_fence()
479 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v5_0_ring_emit_fence()
481 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v5_0_ring_emit_fence()
503 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));  in uvd_v5_0_ring_test_ring()
532 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));  in uvd_v5_0_ring_emit_ib()
534 	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));  in uvd_v5_0_ring_emit_ib()
536 	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));  in uvd_v5_0_ring_emit_ib()
547 		amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));  in uvd_v5_0_ring_insert_nop()