2387 						SISLANDS_SMC_SWSTATE *smc_state)  in si_populate_power_containment_values()  argument
2410 	if (smc_state->levelCount != state->performance_level_count)  in si_populate_power_containment_values()
2415 	smc_state->levels[0].dpm2.MaxPS = 0;  in si_populate_power_containment_values()
2416 	smc_state->levels[0].dpm2.NearTDPDec = 0;  in si_populate_power_containment_values()
2417 	smc_state->levels[0].dpm2.AboveSafeInc = 0;  in si_populate_power_containment_values()
2418 	smc_state->levels[0].dpm2.BelowSafeInc = 0;  in si_populate_power_containment_values()
2419 	smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;  in si_populate_power_containment_values()
2468 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma…  in si_populate_power_containment_values()
2469 		smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;  in si_populate_power_containment_values()
2470 		smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;  in si_populate_power_containment_values()
2471 		smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;  in si_populate_power_containment_values()
2472 		smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);  in si_populate_power_containment_values()
2480 					 SISLANDS_SMC_SWSTATE *smc_state)  in si_populate_sq_ramping_values()  argument
2491 	if (smc_state->levelCount != state->performance_level_count)  in si_populate_sq_ramping_values()
2528 		smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);  in si_populate_sq_ramping_values()
2529 		smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);  in si_populate_sq_ramping_values()
5426 			       SISLANDS_SMC_SWSTATE *smc_state)  in si_populate_smc_sp()  argument
5433 		smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);  in si_populate_smc_sp()
5435 	smc_state->levels[ps->performance_level_count - 1].bSP =  in si_populate_smc_sp()
5550 			     SISLANDS_SMC_SWSTATE *smc_state)  in si_populate_smc_t()  argument
5564 		smc_state->levels[0].aT = cpu_to_be32(a_t);  in si_populate_smc_t()
5568 	smc_state->levels[0].aT = cpu_to_be32(0);  in si_populate_smc_t()
5584 		a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;  in si_populate_smc_t()
5586 		smc_state->levels[i].aT = cpu_to_be32(a_t);  in si_populate_smc_t()
5591 		smc_state->levels[i + 1].aT = cpu_to_be32(a_t);  in si_populate_smc_t()
5653 					 SISLANDS_SMC_SWSTATE *smc_state)  in si_convert_power_state_to_smc()  argument
5671 			smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;  in si_convert_power_state_to_smc()
5677 		smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;  in si_convert_power_state_to_smc()
5679 	smc_state->levelCount = 0;  in si_convert_power_state_to_smc()
5684 					smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;  in si_convert_power_state_to_smc()
5686 					smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;  in si_convert_power_state_to_smc()
5691 						    &smc_state->levels[i]);  in si_convert_power_state_to_smc()
5692 		smc_state->levels[i].arbRefreshState =  in si_convert_power_state_to_smc()
5699 			smc_state->levels[i].displayWatermark =  in si_convert_power_state_to_smc()
5703 			smc_state->levels[i].displayWatermark = (i < 2) ?  in si_convert_power_state_to_smc()
5707 			smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;  in si_convert_power_state_to_smc()
5709 			smc_state->levels[i].ACIndex = 0;  in si_convert_power_state_to_smc()
5711 		smc_state->levelCount++;  in si_convert_power_state_to_smc()
5718 	si_populate_smc_sp(adev, amdgpu_state, smc_state);  in si_convert_power_state_to_smc()
5720 	ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);  in si_convert_power_state_to_smc()
5724 	ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);  in si_convert_power_state_to_smc()
5728 	return si_populate_smc_t(adev, amdgpu_state, smc_state);  in si_convert_power_state_to_smc()
5742 	SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;  in si_upload_sw_state()  local
5744 	memset(smc_state, 0, state_size);  in si_upload_sw_state()
5746 	ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);  in si_upload_sw_state()
5750 	return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,  in si_upload_sw_state()
5763 		SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;  in si_upload_ulv_state()  local
5766 		memset(smc_state, 0, state_size);  in si_upload_ulv_state()
5768 		ret = si_populate_ulv_state(adev, smc_state);  in si_upload_ulv_state()
5770 			ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,  in si_upload_ulv_state()