Lines Matching refs:si_pi
1983 struct si_power_info *si_pi = si_get_pi(adev); in si_initialize_powertune_defaults() local
1987 si_pi->cac_weights = cac_weights_tahiti; in si_initialize_powertune_defaults()
1988 si_pi->lcac_config = lcac_tahiti; in si_initialize_powertune_defaults()
1989 si_pi->cac_override = cac_override_tahiti; in si_initialize_powertune_defaults()
1990 si_pi->powertune_data = &powertune_data_tahiti; in si_initialize_powertune_defaults()
1991 si_pi->dte_data = dte_data_tahiti; in si_initialize_powertune_defaults()
1995 si_pi->dte_data.enable_dte_by_default = true; in si_initialize_powertune_defaults()
1998 si_pi->dte_data = dte_data_new_zealand; in si_initialize_powertune_defaults()
2004 si_pi->dte_data = dte_data_aruba_pro; in si_initialize_powertune_defaults()
2008 si_pi->dte_data = dte_data_malta; in si_initialize_powertune_defaults()
2012 si_pi->dte_data = dte_data_tahiti_pro; in si_initialize_powertune_defaults()
2016 if (si_pi->dte_data.enable_dte_by_default == true) in si_initialize_powertune_defaults()
2021 si_pi->cac_weights = cac_weights_pitcairn; in si_initialize_powertune_defaults()
2022 si_pi->lcac_config = lcac_pitcairn; in si_initialize_powertune_defaults()
2023 si_pi->cac_override = cac_override_pitcairn; in si_initialize_powertune_defaults()
2024 si_pi->powertune_data = &powertune_data_pitcairn; in si_initialize_powertune_defaults()
2029 si_pi->dte_data = dte_data_curacao_xt; in si_initialize_powertune_defaults()
2034 si_pi->dte_data = dte_data_curacao_pro; in si_initialize_powertune_defaults()
2039 si_pi->dte_data = dte_data_neptune_xt; in si_initialize_powertune_defaults()
2043 si_pi->dte_data = dte_data_pitcairn; in si_initialize_powertune_defaults()
2047 si_pi->lcac_config = lcac_cape_verde; in si_initialize_powertune_defaults()
2048 si_pi->cac_override = cac_override_cape_verde; in si_initialize_powertune_defaults()
2049 si_pi->powertune_data = &powertune_data_cape_verde; in si_initialize_powertune_defaults()
2056 si_pi->cac_weights = cac_weights_cape_verde_pro; in si_initialize_powertune_defaults()
2057 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
2060 si_pi->cac_weights = cac_weights_cape_verde_pro; in si_initialize_powertune_defaults()
2061 si_pi->dte_data = dte_data_sun_xt; in si_initialize_powertune_defaults()
2066 si_pi->cac_weights = cac_weights_heathrow; in si_initialize_powertune_defaults()
2067 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
2071 si_pi->cac_weights = cac_weights_chelsea_xt; in si_initialize_powertune_defaults()
2072 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
2075 si_pi->cac_weights = cac_weights_chelsea_pro; in si_initialize_powertune_defaults()
2076 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
2079 si_pi->cac_weights = cac_weights_heathrow; in si_initialize_powertune_defaults()
2080 si_pi->dte_data = dte_data_venus_xtx; in si_initialize_powertune_defaults()
2083 si_pi->cac_weights = cac_weights_heathrow; in si_initialize_powertune_defaults()
2084 si_pi->dte_data = dte_data_venus_xt; in si_initialize_powertune_defaults()
2090 si_pi->cac_weights = cac_weights_chelsea_pro; in si_initialize_powertune_defaults()
2091 si_pi->dte_data = dte_data_venus_pro; in si_initialize_powertune_defaults()
2094 si_pi->cac_weights = cac_weights_cape_verde; in si_initialize_powertune_defaults()
2095 si_pi->dte_data = dte_data_cape_verde; in si_initialize_powertune_defaults()
2099 si_pi->lcac_config = lcac_mars_pro; in si_initialize_powertune_defaults()
2100 si_pi->cac_override = cac_override_oland; in si_initialize_powertune_defaults()
2101 si_pi->powertune_data = &powertune_data_mars_pro; in si_initialize_powertune_defaults()
2102 si_pi->dte_data = dte_data_mars_pro; in si_initialize_powertune_defaults()
2109 si_pi->cac_weights = cac_weights_mars_pro; in si_initialize_powertune_defaults()
2116 si_pi->cac_weights = cac_weights_mars_xt; in si_initialize_powertune_defaults()
2122 si_pi->cac_weights = cac_weights_oland_pro; in si_initialize_powertune_defaults()
2126 si_pi->cac_weights = cac_weights_oland_xt; in si_initialize_powertune_defaults()
2130 si_pi->cac_weights = cac_weights_oland; in si_initialize_powertune_defaults()
2131 si_pi->lcac_config = lcac_oland; in si_initialize_powertune_defaults()
2132 si_pi->cac_override = cac_override_oland; in si_initialize_powertune_defaults()
2133 si_pi->powertune_data = &powertune_data_oland; in si_initialize_powertune_defaults()
2134 si_pi->dte_data = dte_data_oland; in si_initialize_powertune_defaults()
2138 si_pi->cac_weights = cac_weights_hainan; in si_initialize_powertune_defaults()
2139 si_pi->lcac_config = lcac_oland; in si_initialize_powertune_defaults()
2140 si_pi->cac_override = cac_override_oland; in si_initialize_powertune_defaults()
2141 si_pi->powertune_data = &powertune_data_hainan; in si_initialize_powertune_defaults()
2142 si_pi->dte_data = dte_data_sun_xt; in si_initialize_powertune_defaults()
2152 si_pi->enable_dte = false; in si_initialize_powertune_defaults()
2154 if (si_pi->powertune_data->enable_powertune_by_default) { in si_initialize_powertune_defaults()
2157 if (si_pi->dte_data.enable_dte_by_default) { in si_initialize_powertune_defaults()
2158 si_pi->enable_dte = true; in si_initialize_powertune_defaults()
2160 si_update_dte_from_pl2(adev, &si_pi->dte_data); in si_initialize_powertune_defaults()
2171 si_pi->dyn_powertune_data.l2_lta_window_size = in si_initialize_powertune_defaults()
2172 si_pi->powertune_data->l2_lta_window_size_default; in si_initialize_powertune_defaults()
2173 si_pi->dyn_powertune_data.lts_truncate = in si_initialize_powertune_defaults()
2174 si_pi->powertune_data->lts_truncate_default; in si_initialize_powertune_defaults()
2177 si_pi->dyn_powertune_data.l2_lta_window_size = 0; in si_initialize_powertune_defaults()
2178 si_pi->dyn_powertune_data.lts_truncate = 0; in si_initialize_powertune_defaults()
2181 si_pi->dyn_powertune_data.disable_uvd_powertune = false; in si_initialize_powertune_defaults()
2251 struct si_power_info *si_pi = si_get_pi(adev); in si_populate_smc_tdp_limits() local
2254 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; in si_populate_smc_tdp_limits()
2283 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + in si_populate_smc_tdp_limits()
2287 si_pi->sram_end); in si_populate_smc_tdp_limits()
2291 if (si_pi->enable_ppm) { in si_populate_smc_tdp_limits()
2292 papm_parm = &si_pi->papm_parm; in si_populate_smc_tdp_limits()
2301 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start, in si_populate_smc_tdp_limits()
2304 si_pi->sram_end); in si_populate_smc_tdp_limits()
2316 struct si_power_info *si_pi = si_get_pi(adev); in si_populate_smc_tdp_limits_2() local
2319 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; in si_populate_smc_tdp_limits_2()
2331 (si_pi->state_table_start + in si_populate_smc_tdp_limits_2()
2336 si_pi->sram_end); in si_populate_smc_tdp_limits_2()
2369 struct si_power_info *si_pi = si_get_pi(adev); in si_should_disable_uvd_powertune() local
2371 if (si_pi->dyn_powertune_data.disable_uvd_powertune && in si_should_disable_uvd_powertune()
2567 struct si_power_info *si_pi = si_get_pi(adev); in si_initialize_smc_dte_tables() local
2569 struct si_dte_data *dte_data = &si_pi->dte_data; in si_initialize_smc_dte_tables()
2576 si_pi->enable_dte = false; in si_initialize_smc_dte_tables()
2578 if (si_pi->enable_dte == false) in si_initialize_smc_dte_tables()
2586 si_pi->enable_dte = false; in si_initialize_smc_dte_tables()
2623 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start, in si_initialize_smc_dte_tables()
2626 si_pi->sram_end); in si_initialize_smc_dte_tables()
2635 struct si_power_info *si_pi = si_get_pi(adev); in si_get_cac_std_voltage_max_min() local
2654 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) in si_get_cac_std_voltage_max_min()
2657 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; in si_get_cac_std_voltage_max_min()
2681 struct si_power_info *si_pi = si_get_pi(adev); in si_init_dte_leakage_table() local
2698 &si_pi->powertune_data->leakage_coefficients, in si_init_dte_leakage_table()
2701 si_pi->dyn_powertune_data.cac_leakage, in si_init_dte_leakage_table()
2720 struct si_power_info *si_pi = si_get_pi(adev); in si_init_simplified_leakage_table() local
2733 &si_pi->powertune_data->leakage_coefficients, in si_init_simplified_leakage_table()
2734 si_pi->powertune_data->fixed_kt, in si_init_simplified_leakage_table()
2736 si_pi->dyn_powertune_data.cac_leakage, in si_init_simplified_leakage_table()
2754 struct si_power_info *si_pi = si_get_pi(adev); in si_initialize_smc_cac_tables() local
2770 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); in si_initialize_smc_cac_tables()
2773 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage; in si_initialize_smc_cac_tables()
2774 si_pi->dyn_powertune_data.dc_pwr_value = in si_initialize_smc_cac_tables()
2775 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; in si_initialize_smc_cac_tables()
2776 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev); in si_initialize_smc_cac_tables()
2777 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; in si_initialize_smc_cac_tables()
2779 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; in si_initialize_smc_cac_tables()
2790 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) in si_initialize_smc_cac_tables()
2802 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); in si_initialize_smc_cac_tables()
2803 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; in si_initialize_smc_cac_tables()
2804 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; in si_initialize_smc_cac_tables()
2808 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); in si_initialize_smc_cac_tables()
2812 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; in si_initialize_smc_cac_tables()
2816 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start, in si_initialize_smc_cac_tables()
2819 si_pi->sram_end); in si_initialize_smc_cac_tables()
2879 struct si_power_info *si_pi = si_get_pi(adev); in si_initialize_hardware_cac_manager() local
2886 ret = si_program_cac_config_registers(adev, si_pi->lcac_config); in si_initialize_hardware_cac_manager()
2889 ret = si_program_cac_config_registers(adev, si_pi->cac_override); in si_initialize_hardware_cac_manager()
2892 ret = si_program_cac_config_registers(adev, si_pi->cac_weights); in si_initialize_hardware_cac_manager()
2904 struct si_power_info *si_pi = si_get_pi(adev); in si_enable_smc_cac() local
2925 if (si_pi->enable_dte) { in si_enable_smc_cac()
2932 if (si_pi->enable_dte) in si_enable_smc_cac()
2949 struct si_power_info *si_pi = si_get_pi(adev); in si_init_smc_spll_table() local
2959 if (si_pi->spll_table_start == 0) in si_init_smc_spll_table()
3004 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start, in si_init_smc_spll_table()
3007 si_pi->sram_end); in si_init_smc_spll_table()
3021 struct si_power_info *si_pi = si_get_pi(adev); in si_get_lower_of_leakage_and_vce_voltage() local
3024 for (i = 0; i < si_pi->leakage_voltage.count; i++){ in si_get_lower_of_leakage_and_vce_voltage()
3025 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) in si_get_lower_of_leakage_and_vce_voltage()
3026 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; in si_get_lower_of_leakage_and_vce_voltage()
3029 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) in si_get_lower_of_leakage_and_vce_voltage()
3646 struct si_power_info *si_pi = si_get_pi(adev);
3649 si_pi->soft_regs_start + reg_offset, value,
3650 si_pi->sram_end);
3657 struct si_power_info *si_pi = si_get_pi(adev); in si_write_smc_soft_register() local
3660 si_pi->soft_regs_start + reg_offset, in si_write_smc_soft_register()
3661 value, si_pi->sram_end); in si_write_smc_soft_register()
3694 struct si_power_info *si_pi = si_get_pi(adev); in si_get_leakage_vddc() local
3702 si_pi->leakage_voltage.entries[count].voltage = vddc; in si_get_leakage_vddc()
3703 si_pi->leakage_voltage.entries[count].leakage_index = in si_get_leakage_vddc()
3708 si_pi->leakage_voltage.count = count; in si_get_leakage_vddc()
3714 struct si_power_info *si_pi = si_get_pi(adev); in si_get_leakage_voltage_from_leakage_index() local
3729 for (i = 0; i < si_pi->leakage_voltage.count; i++) { in si_get_leakage_voltage_from_leakage_index()
3730 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { in si_get_leakage_voltage_from_leakage_index()
3731 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; in si_get_leakage_voltage_from_leakage_index()
3940 struct si_power_info *si_pi = si_get_pi(adev); in si_process_firmware_header() local
3947 &tmp, si_pi->sram_end); in si_process_firmware_header()
3951 si_pi->state_table_start = tmp; in si_process_firmware_header()
3956 &tmp, si_pi->sram_end); in si_process_firmware_header()
3960 si_pi->soft_regs_start = tmp; in si_process_firmware_header()
3965 &tmp, si_pi->sram_end); in si_process_firmware_header()
3969 si_pi->mc_reg_table_start = tmp; in si_process_firmware_header()
3974 &tmp, si_pi->sram_end); in si_process_firmware_header()
3978 si_pi->fan_table_start = tmp; in si_process_firmware_header()
3983 &tmp, si_pi->sram_end); in si_process_firmware_header()
3987 si_pi->arb_table_start = tmp; in si_process_firmware_header()
3992 &tmp, si_pi->sram_end); in si_process_firmware_header()
3996 si_pi->cac_table_start = tmp; in si_process_firmware_header()
4001 &tmp, si_pi->sram_end); in si_process_firmware_header()
4005 si_pi->dte_table_start = tmp; in si_process_firmware_header()
4010 &tmp, si_pi->sram_end); in si_process_firmware_header()
4014 si_pi->spll_table_start = tmp; in si_process_firmware_header()
4019 &tmp, si_pi->sram_end); in si_process_firmware_header()
4023 si_pi->papm_cfg_table_start = tmp; in si_process_firmware_header()
4030 struct si_power_info *si_pi = si_get_pi(adev); in si_read_clock_registers() local
4032 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in si_read_clock_registers()
4033 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); in si_read_clock_registers()
4034 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); in si_read_clock_registers()
4035 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); in si_read_clock_registers()
4036 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); in si_read_clock_registers()
4037 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in si_read_clock_registers()
4038 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); in si_read_clock_registers()
4039 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in si_read_clock_registers()
4040 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in si_read_clock_registers()
4041 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in si_read_clock_registers()
4042 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); in si_read_clock_registers()
4043 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in si_read_clock_registers()
4044 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); in si_read_clock_registers()
4045 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in si_read_clock_registers()
4046 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); in si_read_clock_registers()
4347 struct si_power_info *si_pi = si_get_pi(adev); in si_upload_firmware() local
4352 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end); in si_upload_firmware()
4424 struct si_power_info *si_pi = si_get_pi(adev); in si_construct_voltage_tables() local
4437 } else if (si_pi->voltage_control_svi2) { in si_construct_voltage_tables()
4458 if (si_pi->vddci_control_svi2) { in si_construct_voltage_tables()
4468 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); in si_construct_voltage_tables()
4475 if (si_pi->mvdd_voltage_table.count == 0) { in si_construct_voltage_tables()
4480 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) in si_construct_voltage_tables()
4483 &si_pi->mvdd_voltage_table); in si_construct_voltage_tables()
4486 if (si_pi->vddc_phase_shed_control) { in si_construct_voltage_tables()
4488 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); in si_construct_voltage_tables()
4490 si_pi->vddc_phase_shed_control = false; in si_construct_voltage_tables()
4492 if ((si_pi->vddc_phase_shed_table.count == 0) || in si_construct_voltage_tables()
4493 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) in si_construct_voltage_tables()
4494 si_pi->vddc_phase_shed_control = false; in si_construct_voltage_tables()
4515 struct si_power_info *si_pi = si_get_pi(adev); in si_populate_smc_voltage_tables() local
4518 if (si_pi->voltage_control_svi2) { in si_populate_smc_voltage_tables()
4520 si_pi->svc_gpio_id); in si_populate_smc_voltage_tables()
4522 si_pi->svd_gpio_id); in si_populate_smc_voltage_tables()
4547 if (si_pi->mvdd_voltage_table.count) { in si_populate_smc_voltage_tables()
4548 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table); in si_populate_smc_voltage_tables()
4551 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); in si_populate_smc_voltage_tables()
4554 if (si_pi->vddc_phase_shed_control) { in si_populate_smc_voltage_tables()
4555 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table, in si_populate_smc_voltage_tables()
4557 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table); in si_populate_smc_voltage_tables()
4560 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); in si_populate_smc_voltage_tables()
4563 (u32)si_pi->vddc_phase_shed_table.phase_delay); in si_populate_smc_voltage_tables()
4565 si_pi->vddc_phase_shed_control = false; in si_populate_smc_voltage_tables()
4597 struct si_power_info *si_pi = si_get_pi(adev); in si_populate_mvdd_value() local
4603 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; in si_populate_mvdd_value()
4605 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); in si_populate_mvdd_value()
4692 struct si_power_info *si_pi = si_get_pi(adev); in si_init_arb_table_index() local
4696 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, in si_init_arb_table_index()
4697 &tmp, si_pi->sram_end); in si_init_arb_table_index()
4704 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start, in si_init_arb_table_index()
4705 tmp, si_pi->sram_end); in si_init_arb_table_index()
4721 struct si_power_info *si_pi = si_get_pi(adev); in si_force_switch_to_arb_f0() local
4725 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, in si_force_switch_to_arb_f0()
4726 &tmp, si_pi->sram_end); in si_force_switch_to_arb_f0()
4787 struct si_power_info *si_pi = si_get_pi(adev); in si_do_program_memory_timing_parameters() local
4797 si_pi->arb_table_start + in si_do_program_memory_timing_parameters()
4802 si_pi->sram_end); in si_do_program_memory_timing_parameters()
4821 struct si_power_info *si_pi = si_get_pi(adev); in si_populate_initial_mvdd_value() local
4824 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table, in si_populate_initial_mvdd_value()
4825 si_pi->mvdd_bootup_value, voltage); in si_populate_initial_mvdd_value()
4837 struct si_power_info *si_pi = si_get_pi(adev); in si_populate_smc_initial_state() local
4842 cpu_to_be32(si_pi->clock_registers.dll_cntl); in si_populate_smc_initial_state()
4844 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); in si_populate_smc_initial_state()
4846 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); in si_populate_smc_initial_state()
4848 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); in si_populate_smc_initial_state()
4850 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); in si_populate_smc_initial_state()
4852 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); in si_populate_smc_initial_state()
4854 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); in si_populate_smc_initial_state()
4856 cpu_to_be32(si_pi->clock_registers.mpll_ss1); in si_populate_smc_initial_state()
4858 cpu_to_be32(si_pi->clock_registers.mpll_ss2); in si_populate_smc_initial_state()
4864 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); in si_populate_smc_initial_state()
4866 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); in si_populate_smc_initial_state()
4868 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); in si_populate_smc_initial_state()
4870 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); in si_populate_smc_initial_state()
4872 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); in si_populate_smc_initial_state()
4874 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); in si_populate_smc_initial_state()
4906 if (si_pi->vddc_phase_shed_control) in si_populate_smc_initial_state()
4919 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; in si_populate_smc_initial_state()
4956 struct si_power_info *si_pi = si_get_pi(adev); in si_populate_smc_acpi_state() local
4957 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; in si_populate_smc_acpi_state()
4958 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; in si_populate_smc_acpi_state()
4959 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; in si_populate_smc_acpi_state()
4960 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; in si_populate_smc_acpi_state()
4961 u32 dll_cntl = si_pi->clock_registers.dll_cntl; in si_populate_smc_acpi_state()
4962 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; in si_populate_smc_acpi_state()
4963 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; in si_populate_smc_acpi_state()
4964 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; in si_populate_smc_acpi_state()
4965 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; in si_populate_smc_acpi_state()
4966 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; in si_populate_smc_acpi_state()
4967 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; in si_populate_smc_acpi_state()
4988 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; in si_populate_smc_acpi_state()
4990 if (si_pi->vddc_phase_shed_control) { in si_populate_smc_acpi_state()
5014 si_pi->sys_pcie_mask, in si_populate_smc_acpi_state()
5015 si_pi->boot_pcie_gen, in si_populate_smc_acpi_state()
5018 if (si_pi->vddc_phase_shed_control) in si_populate_smc_acpi_state()
5057 cpu_to_be32(si_pi->clock_registers.mpll_ss1); in si_populate_smc_acpi_state()
5059 cpu_to_be32(si_pi->clock_registers.mpll_ss2); in si_populate_smc_acpi_state()
5097 struct si_power_info *si_pi = si_get_pi(adev); in si_populate_ulv_state() local
5098 struct si_ulv_param *ulv = &si_pi->ulv; in si_populate_ulv_state()
5126 struct si_power_info *si_pi = si_get_pi(adev); in si_program_ulv_memory_timing_parameters() local
5127 struct si_ulv_param *ulv = &si_pi->ulv; in si_program_ulv_memory_timing_parameters()
5140 si_pi->arb_table_start + in si_program_ulv_memory_timing_parameters()
5145 si_pi->sram_end); in si_program_ulv_memory_timing_parameters()
5159 struct si_power_info *si_pi = si_get_pi(adev); in si_init_smc_table() local
5161 const struct si_ulv_param *ulv = &si_pi->ulv; in si_init_smc_table()
5162 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; in si_init_smc_table()
5239 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start, in si_init_smc_table()
5241 si_pi->sram_end); in si_init_smc_table()
5249 struct si_power_info *si_pi = si_get_pi(adev); in si_calculate_sclk_params() local
5251 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; in si_calculate_sclk_params()
5252 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; in si_calculate_sclk_params()
5253 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; in si_calculate_sclk_params()
5254 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; in si_calculate_sclk_params()
5255 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; in si_calculate_sclk_params()
5256 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; in si_calculate_sclk_params()
5343 struct si_power_info *si_pi = si_get_pi(adev); in si_populate_mclk_value() local
5344 u32 dll_cntl = si_pi->clock_registers.dll_cntl; in si_populate_mclk_value()
5345 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; in si_populate_mclk_value()
5346 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; in si_populate_mclk_value()
5347 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; in si_populate_mclk_value()
5348 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; in si_populate_mclk_value()
5349 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; in si_populate_mclk_value()
5350 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; in si_populate_mclk_value()
5351 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; in si_populate_mclk_value()
5352 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; in si_populate_mclk_value()
5445 struct si_power_info *si_pi = si_get_pi(adev); in si_convert_power_level_to_smc() local
5452 (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID)) in si_convert_power_level_to_smc()
5453 level->gen2PCIE = (u8)si_pi->force_pcie_gen; in si_convert_power_level_to_smc()
5530 if (si_pi->vddc_phase_shed_control) { in si_convert_power_level_to_smc()
5541 level->MaxPoweredUpCU = si_pi->max_cu; in si_convert_power_level_to_smc()
5599 struct si_power_info *si_pi = si_get_pi(adev); in si_disable_ulv() local
5600 struct si_ulv_param *ulv = &si_pi->ulv; in si_disable_ulv()
5612 const struct si_power_info *si_pi = si_get_pi(adev); in si_is_state_ulv_compatible() local
5613 const struct si_ulv_param *ulv = &si_pi->ulv; in si_is_state_ulv_compatible()
5640 const struct si_power_info *si_pi = si_get_pi(adev); in si_set_power_state_conditionally_enable_ulv() local
5641 const struct si_ulv_param *ulv = &si_pi->ulv; in si_set_power_state_conditionally_enable_ulv()
5657 struct si_power_info *si_pi = si_get_pi(adev); in si_convert_power_state_to_smc() local
5682 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { in si_convert_power_state_to_smc()
5734 struct si_power_info *si_pi = si_get_pi(adev); in si_upload_sw_state() local
5737 u32 address = si_pi->state_table_start + in si_upload_sw_state()
5742 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; in si_upload_sw_state()
5751 state_size, si_pi->sram_end); in si_upload_sw_state()
5756 struct si_power_info *si_pi = si_get_pi(adev); in si_upload_ulv_state() local
5757 struct si_ulv_param *ulv = &si_pi->ulv; in si_upload_ulv_state()
5761 u32 address = si_pi->state_table_start + in si_upload_ulv_state()
5763 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; in si_upload_ulv_state()
5771 state_size, si_pi->sram_end); in si_upload_ulv_state()
5989 struct si_power_info *si_pi = si_get_pi(adev); in si_initialize_mc_reg_table() local
5991 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; in si_initialize_mc_reg_table()
6040 struct si_power_info *si_pi = si_get_pi(adev); in si_populate_mc_reg_addresses() local
6043 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { in si_populate_mc_reg_addresses()
6044 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { in si_populate_mc_reg_addresses()
6048 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); in si_populate_mc_reg_addresses()
6050 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); in si_populate_mc_reg_addresses()
6075 struct si_power_info *si_pi = si_get_pi(adev); in si_convert_mc_reg_table_entry_to_smc() local
6078 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { in si_convert_mc_reg_table_entry_to_smc()
6079 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in si_convert_mc_reg_table_entry_to_smc()
6083 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) in si_convert_mc_reg_table_entry_to_smc()
6086 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], in si_convert_mc_reg_table_entry_to_smc()
6087 mc_reg_table_data, si_pi->mc_reg_table.last, in si_convert_mc_reg_table_entry_to_smc()
6088 si_pi->mc_reg_table.valid_flag); in si_convert_mc_reg_table_entry_to_smc()
6109 struct si_power_info *si_pi = si_get_pi(adev); in si_populate_mc_reg_table() local
6110 struct si_ulv_param *ulv = &si_pi->ulv; in si_populate_mc_reg_table()
6111 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; in si_populate_mc_reg_table()
6122 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], in si_populate_mc_reg_table()
6124 si_pi->mc_reg_table.last, in si_populate_mc_reg_table()
6125 si_pi->mc_reg_table.valid_flag); in si_populate_mc_reg_table()
6131 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], in si_populate_mc_reg_table()
6133 si_pi->mc_reg_table.last, in si_populate_mc_reg_table()
6134 si_pi->mc_reg_table.valid_flag); in si_populate_mc_reg_table()
6138 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start, in si_populate_mc_reg_table()
6140 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); in si_populate_mc_reg_table()
6147 struct si_power_info *si_pi = si_get_pi(adev); in si_upload_mc_reg_table() local
6148 u32 address = si_pi->mc_reg_table_start + in si_upload_mc_reg_table()
6151 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; in si_upload_mc_reg_table()
6160 si_pi->sram_end); in si_upload_mc_reg_table()
6200 struct si_power_info *si_pi = si_get_pi(adev); in si_request_link_speed_change_before_state_change() local
6204 if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID) in si_request_link_speed_change_before_state_change()
6207 current_link_speed = si_pi->force_pcie_gen; in si_request_link_speed_change_before_state_change()
6209 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; in si_request_link_speed_change_before_state_change()
6210 si_pi->pspp_notify_required = false; in si_request_link_speed_change_before_state_change()
6217 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2; in si_request_link_speed_change_before_state_change()
6227 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev); in si_request_link_speed_change_before_state_change()
6232 si_pi->pspp_notify_required = true; in si_request_link_speed_change_before_state_change()
6240 struct si_power_info *si_pi = si_get_pi(adev); in si_notify_link_speed_change_after_state_change() local
6244 if (si_pi->pspp_notify_required) { in si_notify_link_speed_change_after_state_change()
6283 struct si_power_info *si_pi = si_get_pi(adev); in si_set_max_cu_value() local
6292 si_pi->max_cu = 10; in si_set_max_cu_value()
6298 si_pi->max_cu = 8; in si_set_max_cu_value()
6306 si_pi->max_cu = 10; in si_set_max_cu_value()
6311 si_pi->max_cu = 8; in si_set_max_cu_value()
6314 si_pi->max_cu = 0; in si_set_max_cu_value()
6318 si_pi->max_cu = 0; in si_set_max_cu_value()
6445 struct si_power_info *si_pi = si_get_pi(adev); in si_fan_ctrl_set_static_mode() local
6448 if (si_pi->fan_ctrl_is_in_default_mode) { in si_fan_ctrl_set_static_mode()
6450 si_pi->fan_ctrl_default_mode = tmp; in si_fan_ctrl_set_static_mode()
6452 si_pi->t_min = tmp; in si_fan_ctrl_set_static_mode()
6453 si_pi->fan_ctrl_is_in_default_mode = false; in si_fan_ctrl_set_static_mode()
6467 struct si_power_info *si_pi = si_get_pi(adev); in si_thermal_setup_fan_table() local
6476 if (!si_pi->fan_table_start) { in si_thermal_setup_fan_table()
6521 si_pi->fan_table_start, in si_thermal_setup_fan_table()
6524 si_pi->sram_end); in si_thermal_setup_fan_table()
6536 struct si_power_info *si_pi = si_get_pi(adev); in si_fan_ctrl_start_smc_fan_control() local
6541 si_pi->fan_is_controlled_by_smc = true; in si_fan_ctrl_start_smc_fan_control()
6550 struct si_power_info *si_pi = si_get_pi(adev); in si_fan_ctrl_stop_smc_fan_control() local
6556 si_pi->fan_is_controlled_by_smc = false; in si_fan_ctrl_stop_smc_fan_control()
6593 struct si_power_info *si_pi = si_get_pi(adev); in si_dpm_set_fan_speed_percent() local
6601 if (si_pi->fan_is_controlled_by_smc) in si_dpm_set_fan_speed_percent()
6644 struct si_power_info *si_pi = si_get_pi(adev); in si_dpm_get_fan_control_mode() local
6647 if (si_pi->fan_is_controlled_by_smc) in si_dpm_get_fan_control_mode()
6708 struct si_power_info *si_pi = si_get_pi(adev); in si_fan_ctrl_set_default_mode() local
6711 if (!si_pi->fan_ctrl_is_in_default_mode) { in si_fan_ctrl_set_default_mode()
6713 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); in si_fan_ctrl_set_default_mode()
6717 tmp |= TMIN(si_pi->t_min); in si_fan_ctrl_set_default_mode()
6719 si_pi->fan_ctrl_is_in_default_mode = true; in si_fan_ctrl_set_default_mode()
6785 struct si_power_info *si_pi = si_get_pi(adev); in si_dpm_enable() local
6791 if (pi->voltage_control || si_pi->voltage_control_svi2) in si_dpm_enable()
6795 if (pi->voltage_control || si_pi->voltage_control_svi2) { in si_dpm_enable()
7138 struct si_power_info *si_pi = si_get_pi(adev); in si_parse_pplib_clock_info() local
7155 si_pi->sys_pcie_mask, in si_parse_pplib_clock_info()
7156 si_pi->boot_pcie_gen, in si_parse_pplib_clock_info()
7168 si_pi->acpi_pcie_gen = pl->pcie_gen; in si_parse_pplib_clock_info()
7174 si_pi->ulv.supported = false; in si_parse_pplib_clock_info()
7175 si_pi->ulv.pl = *pl; in si_parse_pplib_clock_info()
7176 si_pi->ulv.one_pcie_lane_in_ulv = false; in si_parse_pplib_clock_info()
7177 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; in si_parse_pplib_clock_info()
7178 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; in si_parse_pplib_clock_info()
7179 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; in si_parse_pplib_clock_info()
7196 si_pi->mvdd_bootup_value = mvdd; in si_parse_pplib_clock_info()
7310 struct si_power_info *si_pi; in si_dpm_init() local
7314 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); in si_dpm_init()
7315 if (si_pi == NULL) in si_dpm_init()
7317 adev->pm.dpm.priv = si_pi; in si_dpm_init()
7318 ni_pi = &si_pi->ni; in si_dpm_init()
7322 si_pi->sys_pcie_mask = in si_dpm_init()
7324 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; in si_dpm_init()
7325 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); in si_dpm_init()
7396 si_pi->voltage_control_svi2 = in si_dpm_init()
7399 if (si_pi->voltage_control_svi2) in si_dpm_init()
7401 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); in si_dpm_init()
7412 si_pi->vddci_control_svi2 = in si_dpm_init()
7416 si_pi->vddc_phase_shed_control = in si_dpm_init()
7429 si_pi->sclk_deep_sleep_above_low = false; in si_dpm_init()
7446 si_pi->sram_end = SMC_RAM_END; in si_dpm_init()
7464 si_pi->fan_ctrl_is_in_default_mode = true; in si_dpm_init()