Lines Matching refs:performance_levels
2422 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()
2423 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()
2441 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2442 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2448 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2457 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
2516 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
3183 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock()
3184 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_before_set_eng_clock()
3201 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < in ni_set_uvd_clock_after_set_eng_clock()
3202 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_after_set_eng_clock()
3491 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) in si_apply_state_adjust_rules()
3492 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; in si_apply_state_adjust_rules()
3496 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
3497 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3498 if (ps->performance_levels[i].sclk > max_limits->sclk) in si_apply_state_adjust_rules()
3499 ps->performance_levels[i].sclk = max_limits->sclk; in si_apply_state_adjust_rules()
3500 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
3501 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3502 if (ps->performance_levels[i].vddci > max_limits->vddci) in si_apply_state_adjust_rules()
3503 ps->performance_levels[i].vddci = max_limits->vddci; in si_apply_state_adjust_rules()
3517 if (ps->performance_levels[i].sclk > max_sclk_vddc) in si_apply_state_adjust_rules()
3518 ps->performance_levels[i].sclk = max_sclk_vddc; in si_apply_state_adjust_rules()
3521 if (ps->performance_levels[i].mclk > max_mclk_vddci) in si_apply_state_adjust_rules()
3522 ps->performance_levels[i].mclk = max_mclk_vddci; in si_apply_state_adjust_rules()
3525 if (ps->performance_levels[i].mclk > max_mclk_vddc) in si_apply_state_adjust_rules()
3526 ps->performance_levels[i].mclk = max_mclk_vddc; in si_apply_state_adjust_rules()
3529 if (ps->performance_levels[i].mclk > max_mclk) in si_apply_state_adjust_rules()
3530 ps->performance_levels[i].mclk = max_mclk; in si_apply_state_adjust_rules()
3533 if (ps->performance_levels[i].sclk > max_sclk) in si_apply_state_adjust_rules()
3534 ps->performance_levels[i].sclk = max_sclk; in si_apply_state_adjust_rules()
3541 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
3542 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; in si_apply_state_adjust_rules()
3544 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3545 vddci = ps->performance_levels[0].vddci; in si_apply_state_adjust_rules()
3549 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; in si_apply_state_adjust_rules()
3550 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; in si_apply_state_adjust_rules()
3552 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3553 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3564 ps->performance_levels[0].sclk = sclk; in si_apply_state_adjust_rules()
3565 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3566 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3567 ps->performance_levels[0].vddci = vddci; in si_apply_state_adjust_rules()
3570 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3572 if (sclk < ps->performance_levels[i].sclk) in si_apply_state_adjust_rules()
3573 sclk = ps->performance_levels[i].sclk; in si_apply_state_adjust_rules()
3576 ps->performance_levels[i].sclk = sclk; in si_apply_state_adjust_rules()
3577 ps->performance_levels[i].vddc = vddc; in si_apply_state_adjust_rules()
3581 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in si_apply_state_adjust_rules()
3582 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in si_apply_state_adjust_rules()
3583 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) in si_apply_state_adjust_rules()
3584 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in si_apply_state_adjust_rules()
3589 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3591 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3592 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3595 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
3596 ps->performance_levels[i].vddci = vddci; in si_apply_state_adjust_rules()
3600 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in si_apply_state_adjust_rules()
3601 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in si_apply_state_adjust_rules()
3602 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) in si_apply_state_adjust_rules()
3603 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; in si_apply_state_adjust_rules()
3609 &ps->performance_levels[i]); in si_apply_state_adjust_rules()
3612 if (ps->performance_levels[i].vddc < min_vce_voltage) in si_apply_state_adjust_rules()
3613 ps->performance_levels[i].vddc = min_vce_voltage; in si_apply_state_adjust_rules()
3615 ps->performance_levels[i].sclk, in si_apply_state_adjust_rules()
3616 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3618 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3619 max_limits->vddci, &ps->performance_levels[i].vddci); in si_apply_state_adjust_rules()
3621 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3622 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3625 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3631 &ps->performance_levels[i].vddc, in si_apply_state_adjust_rules()
3632 &ps->performance_levels[i].vddci); in si_apply_state_adjust_rules()
3637 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
4793 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); in si_do_program_memory_timing_parameters()
4861 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4877 cpu_to_be32(initial_state->performance_levels[0].sclk); in si_populate_smc_initial_state()
4885 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4903 initial_state->performance_levels[0].vddci, in si_populate_smc_initial_state()
4909 initial_state->performance_levels[0].vddc, in si_populate_smc_initial_state()
4910 initial_state->performance_levels[0].sclk, in si_populate_smc_initial_state()
4911 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4924 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4926 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
5574 state->performance_levels[i + 1].sclk, in si_populate_smc_t()
5575 state->performance_levels[i].sclk, in si_populate_smc_t()
5617 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
5666 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; in si_convert_power_state_to_smc()
5690 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i], in si_convert_power_state_to_smc()
5700 (state->performance_levels[i].sclk < threshold) ? in si_convert_power_state_to_smc()
6100 &state->performance_levels[i], in si_convert_mc_reg_table_to_smc()
6119 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0], in si_populate_mc_reg_table()
6179 pcie_speed = state->performance_levels[i].pcie_gen; in si_get_maximum_link_speed()
7141 struct rv7xx_pl *pl = &ps->performance_levels[index]; in si_parse_pplib_clock_info()
7497 pl = &ps->performance_levels[current_index]; in si_dpm_debugfs_print_current_performance_level()
7877 return requested_state->performance_levels[0].sclk; in si_dpm_get_sclk()
7879 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; in si_dpm_get_sclk()
7889 return requested_state->performance_levels[0].mclk; in si_dpm_get_mclk()
7891 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; in si_dpm_get_mclk()
7907 pl = &ps->performance_levels[i]; in si_dpm_print_power_state()
7969 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]), in si_check_state_equal()
7970 &(si_rps->performance_levels[i]))) { in si_check_state_equal()
8002 sclk = ps->performance_levels[pl_index].sclk; in si_dpm_read_sensor()
8010 mclk = ps->performance_levels[pl_index].mclk; in si_dpm_read_sensor()