3149 	struct si_ps *new_ps = si_get_ps(rps);  in ni_update_current_ps()  local
3154 	ni_pi->current_ps = *new_ps;  in ni_update_current_ps()
3162 	struct si_ps *new_ps = si_get_ps(rps);  in ni_update_requested_ps()  local
3167 	ni_pi->requested_ps = *new_ps;  in ni_update_requested_ps()
3173 					   struct amdgpu_ps *new_ps,  in ni_set_uvd_clock_before_set_eng_clock()  argument
3176 	struct si_ps *new_state = si_get_ps(new_ps);  in ni_set_uvd_clock_before_set_eng_clock()
3179 	if ((new_ps->vclk == old_ps->vclk) &&  in ni_set_uvd_clock_before_set_eng_clock()
3180 	    (new_ps->dclk == old_ps->dclk))  in ni_set_uvd_clock_before_set_eng_clock()
3187 	amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_before_set_eng_clock()
3191 					  struct amdgpu_ps *new_ps,  in ni_set_uvd_clock_after_set_eng_clock()  argument
3194 	struct si_ps *new_state = si_get_ps(new_ps);  in ni_set_uvd_clock_after_set_eng_clock()
3197 	if ((new_ps->vclk == old_ps->vclk) &&  in ni_set_uvd_clock_after_set_eng_clock()
3198 	    (new_ps->dclk == old_ps->dclk))  in ni_set_uvd_clock_after_set_eng_clock()
3205 	amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_after_set_eng_clock()
6943 	struct amdgpu_ps *new_ps = &requested_ps;  in si_dpm_pre_set_power_state()  local
6945 	ni_update_requested_ps(adev, new_ps);  in si_dpm_pre_set_power_state()
6953 	struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;  in si_power_control_set_level()  local
6962 	ret = si_populate_smc_tdp_limits(adev, new_ps);  in si_power_control_set_level()
6965 	ret = si_populate_smc_tdp_limits_2(adev, new_ps);  in si_power_control_set_level()
6981 	struct amdgpu_ps *new_ps = &eg_pi->requested_rps;  in si_dpm_set_power_state()  local
6996 		si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);  in si_dpm_set_power_state()
6997 	ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);  in si_dpm_set_power_state()
6998 	ret = si_enable_power_containment(adev, new_ps, false);  in si_dpm_set_power_state()
7003 	ret = si_enable_smc_cac(adev, new_ps, false);  in si_dpm_set_power_state()
7013 	ret = si_upload_sw_state(adev, new_ps);  in si_dpm_set_power_state()
7029 		ret = si_upload_mc_reg_table(adev, new_ps);  in si_dpm_set_power_state()
7035 	ret = si_program_memory_timing_parameters(adev, new_ps);  in si_dpm_set_power_state()
7040 	si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);  in si_dpm_set_power_state()
7052 	ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);  in si_dpm_set_power_state()
7054 		si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);  in si_dpm_set_power_state()
7055 	ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);  in si_dpm_set_power_state()
7060 	ret = si_enable_smc_cac(adev, new_ps, true);  in si_dpm_set_power_state()
7065 	ret = si_enable_power_containment(adev, new_ps, true);  in si_dpm_set_power_state()
7084 	struct amdgpu_ps *new_ps = &eg_pi->requested_rps;  in si_dpm_post_set_power_state()  local
7086 	ni_update_current_ps(adev, new_ps);  in si_dpm_post_set_power_state()