Lines Matching refs:dpm
1859 struct si_power_info *pi = adev->pm.dpm.priv; in si_get_pi()
1932 u32 p_limit1 = adev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1933 u32 p_limit2 = adev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
1961 struct rv7xx_power_info *pi = adev->pm.dpm.priv; in rv770_get_pi()
1968 struct ni_power_info *pi = adev->pm.dpm.priv; in ni_get_pi()
2222 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2225 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2228 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2229 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2231 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2232 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit; in si_calculate_adjusted_tdp_limits()
2233 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted) in si_calculate_adjusted_tdp_limits()
2234 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; in si_calculate_adjusted_tdp_limits()
2256 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2269 adev->pm.dpm.tdp_adjustment, in si_populate_smc_tdp_limits()
2326 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); in si_populate_smc_tdp_limits_2()
2328 …cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_… in si_populate_smc_tdp_limits_2()
2380 struct evergreen_power_info *pi = adev->pm.dpm.priv; in evergreen_get_pi()
2494 if (adev->pm.dpm.sq_ramping_threshold == 0) in si_populate_sq_ramping_values()
2516 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2637 &adev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
2773 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage; in si_initialize_smc_cac_tables()
2800 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; in si_initialize_smc_cac_tables()
3041 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
3156 adev->pm.dpm.current_ps = &eg_pi->current_rps; in ni_update_current_ps()
3169 adev->pm.dpm.requested_ps = &eg_pi->requested_rps; in ni_update_requested_ps()
3239 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, in btc_get_valid_mclk()
3246 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, in btc_get_valid_sclk()
3299 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
3303 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / in btc_adjust_clock_combinations()
3304 adev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
3306 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
3310 adev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
3325 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
3327 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta)); in btc_apply_voltage_delta_rules()
3331 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
3333 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta)); in btc_apply_voltage_delta_rules()
3467 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
3468 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
3476 if ((adev->pm.dpm.new_active_crtc_count > 1) || in si_apply_state_adjust_rules()
3486 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_apply_state_adjust_rules()
3488 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()
3508 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3510 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3512 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3557 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in si_apply_state_adjust_rules()
3558 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in si_apply_state_adjust_rules()
3559 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) in si_apply_state_adjust_rules()
3560 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; in si_apply_state_adjust_rules()
3614 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3617 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3620 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3623 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in si_apply_state_adjust_rules()
3637 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in si_apply_state_adjust_rules()
3864 struct amdgpu_ps *rps = adev->pm.dpm.current_ps; in si_dpm_force_performance_level()
3888 adev->pm.dpm.forced_level = level; in si_dpm_force_performance_level()
4109 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time; in si_program_response_times()
4153 if (adev->pm.dpm.new_active_crtc_count > 0) in si_program_display_gap()
4158 if (adev->pm.dpm.new_active_crtc_count > 1) in si_program_display_gap()
4168 if ((adev->pm.dpm.new_active_crtc_count > 0) && in si_program_display_gap()
4169 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) { in si_program_display_gap()
4172 if (adev->pm.dpm.new_active_crtcs & (1 << i)) in si_program_display_gap()
4189 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0); in si_program_display_gap()
4439 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_construct_voltage_tables()
4460 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_construct_voltage_tables()
4556 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) { in si_populate_smc_voltage_tables()
4618 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { in si_get_std_voltage_value()
4619 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { in si_get_std_voltage_value()
4620 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in si_get_std_voltage_value()
4623 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4625 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4627 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4629 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4632 …adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4638 …for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in si_get_std_voltage_value()
4640 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in si_get_std_voltage_value()
4642 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4644 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; in si_get_std_voltage_value()
4647 …adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1]… in si_get_std_voltage_value()
4653 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count) in si_get_std_voltage_value()
4654 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; in si_get_std_voltage_value()
4908 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_initial_state()
4992 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
5020 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_populate_smc_acpi_state()
5160 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps; in si_init_smc_table()
5182 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in si_init_smc_table()
5185 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { in si_init_smc_table()
5190 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in si_init_smc_table()
5196 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) in si_init_smc_table()
5199 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { in si_init_smc_table()
5201 vr_hot_gpio = adev->pm.dpm.backbias_response_time; in si_init_smc_table()
5467 (adev->pm.dpm.new_active_crtc_count <= 2)) { in si_convert_power_level_to_smc()
5532 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, in si_convert_power_level_to_smc()
5622 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { in si_is_state_ulv_compatible()
5624 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { in si_is_state_ulv_compatible()
5626 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) in si_is_state_ulv_compatible()
5782 if (adev->pm.dpm.new_active_crtc_count == 0) in si_upload_smc_data()
5786 if (adev->pm.dpm.new_active_crtcs & (1 << i)) { in si_upload_smc_data()
6358 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in si_patch_dependency_tables_based_on_leakage()
6362 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
6366 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in si_patch_dependency_tables_based_on_leakage()
6437 adev->pm.dpm.thermal.min_temp = low_temp; in si_thermal_set_temperature_range()
6438 adev->pm.dpm.thermal.max_temp = high_temp; in si_thermal_set_temperature_range()
6477 adev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6484 adev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6488 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100; in si_thermal_setup_fan_table()
6492 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min; in si_thermal_setup_fan_table()
6493 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med; in si_thermal_setup_fan_table()
6495 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min; in si_thermal_setup_fan_table()
6496 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med; in si_thermal_setup_fan_table()
6501 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100); in si_thermal_setup_fan_table()
6502 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100); in si_thermal_setup_fan_table()
6503 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100); in si_thermal_setup_fan_table()
6507 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst); in si_thermal_setup_fan_table()
6513 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay * in si_thermal_setup_fan_table()
6528 adev->pm.dpm.fan.ucode_fan_control = false; in si_thermal_setup_fan_table()
6629 if (adev->pm.dpm.fan.ucode_fan_control) in si_dpm_set_fan_control_mode()
6634 if (adev->pm.dpm.fan.ucode_fan_control) in si_dpm_set_fan_control_mode()
6692 if (adev->pm.dpm.fan.ucode_fan_control)
6725 if (adev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_smc_fan_control()
6757 if (adev->pm.dpm.fan.ucode_fan_control) { in si_thermal_start_thermal_controller()
6786 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; in si_dpm_enable()
6917 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; in si_dpm_disable()
6942 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; in si_dpm_pre_set_power_state()
6953 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps; in si_power_control_set_level()
7127 adev->pm.dpm.boot_ps = rps; in si_parse_pplib_non_clock_info()
7129 adev->pm.dpm.uvd_ps = rps; in si_parse_pplib_non_clock_info()
7201 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in si_parse_pplib_clock_info()
7202 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
7203 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in si_parse_pplib_clock_info()
7204 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in si_parse_pplib_clock_info()
7247 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in si_parse_power_table()
7250 if (!adev->pm.dpm.ps) in si_parse_power_table()
7261 kfree(adev->pm.dpm.ps); in si_parse_power_table()
7264 adev->pm.dpm.ps[i].ps_priv = ps; in si_parse_power_table()
7265 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], in si_parse_power_table()
7280 &adev->pm.dpm.ps[i], k, in si_parse_power_table()
7286 adev->pm.dpm.num_ps = state_array->ucNumEntries; in si_parse_power_table()
7289 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { in si_parse_power_table()
7291 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; in si_parse_power_table()
7298 adev->pm.dpm.vce_states[i].sclk = sclk; in si_parse_power_table()
7299 adev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
7317 adev->pm.dpm.priv = si_pi; in si_dpm_init()
7350 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in si_dpm_init()
7354 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in si_dpm_init()
7358 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in si_dpm_init()
7359 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in si_dpm_init()
7360 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in si_dpm_init()
7361 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in si_dpm_init()
7362 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in si_dpm_init()
7363 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in si_dpm_init()
7364 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in si_dpm_init()
7365 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in si_dpm_init()
7366 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in si_dpm_init()
7368 if (adev->pm.dpm.voltage_response_time == 0) in si_dpm_init()
7369 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; in si_dpm_init()
7370 if (adev->pm.dpm.backbias_response_time == 0) in si_dpm_init()
7371 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; in si_dpm_init()
7448 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in si_dpm_init()
7449 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in si_dpm_init()
7450 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in si_dpm_init()
7451 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in si_dpm_init()
7452 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in si_dpm_init()
7453 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in si_dpm_init()
7454 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in si_dpm_init()
7459 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in si_dpm_init()
7460 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
7461 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in si_dpm_init()
7462 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_dpm_init()
7473 if (adev->pm.dpm.ps) in si_dpm_fini()
7474 for (i = 0; i < adev->pm.dpm.num_ps; i++) in si_dpm_fini()
7475 kfree(adev->pm.dpm.ps[i].ps_priv); in si_dpm_fini()
7476 kfree(adev->pm.dpm.ps); in si_dpm_fini()
7477 kfree(adev->pm.dpm.priv); in si_dpm_fini()
7478 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in si_dpm_fini()
7564 adev->pm.dpm.thermal.high_to_low = false; in si_dpm_process_interrupt()
7569 adev->pm.dpm.thermal.high_to_low = true; in si_dpm_process_interrupt()
7577 schedule_work(&adev->pm.dpm.thermal.work); in si_dpm_process_interrupt()
7693 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq); in si_dpm_sw_init()
7697 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq); in si_dpm_sw_init()
7702 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in si_dpm_sw_init()
7703 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in si_dpm_sw_init()
7704 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; in si_dpm_sw_init()
7718 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); in si_dpm_sw_init()
7723 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in si_dpm_sw_init()
7742 flush_work(&adev->pm.dpm.thermal.work); in si_dpm_sw_fini()
7794 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in si_dpm_suspend()
8078 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; in si_dpm_set_irq_funcs()
8079 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs; in si_dpm_set_irq_funcs()