546 	rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);  in sdma_v4_0_ring_get_rptr()
566 		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));  in sdma_v4_0_ring_get_wptr()
592 		u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];  in sdma_v4_0_ring_set_wptr()  local
602 		WRITE_ONCE(*wb, (ring->wptr << 2));  in sdma_v4_0_ring_set_wptr()
635 		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));  in sdma_v4_0_page_ring_get_wptr()
657 		u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];  in sdma_v4_0_page_ring_set_wptr()  local
660 		WRITE_ONCE(*wb, (ring->wptr << 2));  in sdma_v4_0_page_ring_set_wptr()
1006 	       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);  in sdma_v4_0_gfx_resume()
1008 	       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);  in sdma_v4_0_gfx_resume()
1038 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);  in sdma_v4_0_gfx_resume()
1096 	       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);  in sdma_v4_0_page_resume()
1098 	       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);  in sdma_v4_0_page_resume()
1129 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);  in sdma_v4_0_page_resume()
1385 	gpu_addr = adev->wb.gpu_addr + (index * 4);  in sdma_v4_0_ring_test_ring()
1387 	adev->wb.wb[index] = cpu_to_le32(tmp);  in sdma_v4_0_ring_test_ring()
1402 		tmp = le32_to_cpu(adev->wb.wb[index]);  in sdma_v4_0_ring_test_ring()
1438 	gpu_addr = adev->wb.gpu_addr + (index * 4);  in sdma_v4_0_ring_test_ib()
1440 	adev->wb.wb[index] = cpu_to_le32(tmp);  in sdma_v4_0_ring_test_ib()
1468 	tmp = le32_to_cpu(adev->wb.wb[index]);  in sdma_v4_0_ring_test_ib()