353 	return ring->adev->wb.wb[ring->rptr_offs] >> 2;  in sdma_v3_0_ring_get_rptr()
370 		wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;  in sdma_v3_0_ring_get_wptr()
390 		u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];  in sdma_v3_0_ring_set_wptr()  local
392 		WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));  in sdma_v3_0_ring_set_wptr()
395 		u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs];  in sdma_v3_0_ring_set_wptr()  local
397 		WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));  in sdma_v3_0_ring_set_wptr()
695 		       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);  in sdma_v3_0_gfx_resume()
697 		       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);  in sdma_v3_0_gfx_resume()
716 		wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);  in sdma_v3_0_gfx_resume()
832 	gpu_addr = adev->wb.gpu_addr + (index * 4);  in sdma_v3_0_ring_test_ring()
834 	adev->wb.wb[index] = cpu_to_le32(tmp);  in sdma_v3_0_ring_test_ring()
849 		tmp = le32_to_cpu(adev->wb.wb[index]);  in sdma_v3_0_ring_test_ring()
885 	gpu_addr = adev->wb.gpu_addr + (index * 4);  in sdma_v3_0_ring_test_ib()
887 	adev->wb.wb[index] = cpu_to_le32(tmp);  in sdma_v3_0_ring_test_ib()
915 	tmp = le32_to_cpu(adev->wb.wb[index]);  in sdma_v3_0_ring_test_ib()