Lines Matching refs:virt
180 mutex_lock(&adev->virt.dpm_mutex); in xgpu_ai_get_pp_clk()
189 size = strnlen((((char *)adev->virt.fw_reserve.p_pf2vf) + in xgpu_ai_get_pp_clk()
193 strcpy(buf,((char *)adev->virt.fw_reserve.p_pf2vf + val)); in xgpu_ai_get_pp_clk()
207 mutex_unlock(&adev->virt.dpm_mutex); in xgpu_ai_get_pp_clk()
219 mutex_lock(&adev->virt.dpm_mutex); in xgpu_ai_force_dpm_level()
233 mutex_unlock(&adev->virt.dpm_mutex); in xgpu_ai_force_dpm_level()
255 adev->virt.fw_reserve.checksum_key = in xgpu_ai_send_access_requests()
314 struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work); in xgpu_ai_mailbox_flr_work() local
315 struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt); in xgpu_ai_mailbox_flr_work()
374 schedule_work(&adev->virt.flr_work); in xgpu_ai_mailbox_rcv_irq()
405 adev->virt.ack_irq.num_types = 1; in xgpu_ai_mailbox_set_irq_funcs()
406 adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs; in xgpu_ai_mailbox_set_irq_funcs()
407 adev->virt.rcv_irq.num_types = 1; in xgpu_ai_mailbox_set_irq_funcs()
408 adev->virt.rcv_irq.funcs = &xgpu_ai_mailbox_rcv_irq_funcs; in xgpu_ai_mailbox_set_irq_funcs()
415 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq); in xgpu_ai_mailbox_add_irq_id()
419 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_ai_mailbox_add_irq_id()
421 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_add_irq_id()
432 r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_get_irq()
435 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_get_irq()
437 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_get_irq()
441 INIT_WORK(&adev->virt.flr_work, xgpu_ai_mailbox_flr_work); in xgpu_ai_mailbox_get_irq()
448 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_put_irq()
449 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_put_irq()