Lines Matching refs:pi
379 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi() local
381 return pi; in kv_get_pi()
461 struct kv_power_info *pi = kv_get_pi(adev); in kv_do_enable_didt() local
464 if (pi->caps_sq_ramping) { in kv_do_enable_didt()
473 if (pi->caps_db_ramping) { in kv_do_enable_didt()
482 if (pi->caps_td_ramping) { in kv_do_enable_didt()
491 if (pi->caps_tcp_ramping) { in kv_do_enable_didt()
503 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_didt() local
506 if (pi->caps_sq_ramping || in kv_enable_didt()
507 pi->caps_db_ramping || in kv_enable_didt()
508 pi->caps_td_ramping || in kv_enable_didt()
509 pi->caps_tcp_ramping) { in kv_enable_didt()
531 struct kv_power_info *pi = kv_get_pi(adev);
533 if (pi->caps_cac) {
563 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_smc_cac() local
566 if (pi->caps_cac) { in kv_enable_smc_cac()
570 pi->cac_enabled = false; in kv_enable_smc_cac()
572 pi->cac_enabled = true; in kv_enable_smc_cac()
573 } else if (pi->cac_enabled) { in kv_enable_smc_cac()
575 pi->cac_enabled = false; in kv_enable_smc_cac()
584 struct kv_power_info *pi = kv_get_pi(adev); in kv_process_firmware_header() local
590 &tmp, pi->sram_end); in kv_process_firmware_header()
593 pi->dpm_table_start = tmp; in kv_process_firmware_header()
597 &tmp, pi->sram_end); in kv_process_firmware_header()
600 pi->soft_regs_start = tmp; in kv_process_firmware_header()
607 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_dpm_voltage_scaling() local
610 pi->graphics_voltage_change_enable = 1; in kv_enable_dpm_voltage_scaling()
613 pi->dpm_table_start + in kv_enable_dpm_voltage_scaling()
615 &pi->graphics_voltage_change_enable, in kv_enable_dpm_voltage_scaling()
616 sizeof(u8), pi->sram_end); in kv_enable_dpm_voltage_scaling()
623 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_interval() local
626 pi->graphics_interval = 1; in kv_set_dpm_interval()
629 pi->dpm_table_start + in kv_set_dpm_interval()
631 &pi->graphics_interval, in kv_set_dpm_interval()
632 sizeof(u8), pi->sram_end); in kv_set_dpm_interval()
639 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_boot_state() local
643 pi->dpm_table_start + in kv_set_dpm_boot_state()
645 &pi->graphics_boot_level, in kv_set_dpm_boot_state()
646 sizeof(u8), pi->sram_end); in kv_set_dpm_boot_state()
664 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_divider_value() local
673 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
674 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
688 struct kv_power_info *pi = kv_get_pi(adev); in kv_convert_2bit_index_to_voltage() local
690 &pi->sys_info.vid_mapping_table, in kv_convert_2bit_index_to_voltage()
699 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_vid() local
701 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; in kv_set_vid()
702 pi->graphics_level[index].MinVddNb = in kv_set_vid()
710 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_at() local
712 pi->graphics_level[index].AT = cpu_to_be16((u16)at); in kv_set_at()
720 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enable() local
722 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; in kv_dpm_power_level_enable()
782 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_sclk_t() local
786 if (pi->caps_sclk_throttle_low_notification) { in kv_update_sclk_t()
787 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in kv_update_sclk_t()
790 pi->dpm_table_start + in kv_update_sclk_t()
793 sizeof(u32), pi->sram_end); in kv_update_sclk_t()
800 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_bootup_state() local
806 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
807 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
811 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
815 &pi->sys_info.sclk_voltage_mapping_table; in kv_program_bootup_state()
820 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
821 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
825 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
833 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_auto_thermal_throttling() local
836 pi->graphics_therm_throttle_enable = 1; in kv_enable_auto_thermal_throttling()
839 pi->dpm_table_start + in kv_enable_auto_thermal_throttling()
841 &pi->graphics_therm_throttle_enable, in kv_enable_auto_thermal_throttling()
842 sizeof(u8), pi->sram_end); in kv_enable_auto_thermal_throttling()
849 struct kv_power_info *pi = kv_get_pi(adev); in kv_upload_dpm_settings() local
853 pi->dpm_table_start + in kv_upload_dpm_settings()
855 (u8 *)&pi->graphics_level, in kv_upload_dpm_settings()
857 pi->sram_end); in kv_upload_dpm_settings()
863 pi->dpm_table_start + in kv_upload_dpm_settings()
865 &pi->graphics_dpm_level_count, in kv_upload_dpm_settings()
866 sizeof(u8), pi->sram_end); in kv_upload_dpm_settings()
878 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_clk_bypass() local
881 if (pi->caps_enable_dfs_bypass) { in kv_get_clk_bypass()
903 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_uvd_table() local
913 pi->uvd_level_count = 0; in kv_populate_uvd_table()
915 if (pi->high_voltage_t && in kv_populate_uvd_table()
916 (pi->high_voltage_t < table->entries[i].v)) in kv_populate_uvd_table()
919 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
920 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
921 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); in kv_populate_uvd_table()
923 pi->uvd_level[i].VClkBypassCntl = in kv_populate_uvd_table()
925 pi->uvd_level[i].DClkBypassCntl = in kv_populate_uvd_table()
932 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
938 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
940 pi->uvd_level_count++; in kv_populate_uvd_table()
944 pi->dpm_table_start + in kv_populate_uvd_table()
946 (u8 *)&pi->uvd_level_count, in kv_populate_uvd_table()
947 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
951 pi->uvd_interval = 1; in kv_populate_uvd_table()
954 pi->dpm_table_start + in kv_populate_uvd_table()
956 &pi->uvd_interval, in kv_populate_uvd_table()
957 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
962 pi->dpm_table_start + in kv_populate_uvd_table()
964 (u8 *)&pi->uvd_level, in kv_populate_uvd_table()
966 pi->sram_end); in kv_populate_uvd_table()
974 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_vce_table() local
984 pi->vce_level_count = 0; in kv_populate_vce_table()
986 if (pi->high_voltage_t && in kv_populate_vce_table()
987 pi->high_voltage_t < table->entries[i].v) in kv_populate_vce_table()
990 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
991 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_vce_table()
993 pi->vce_level[i].ClkBypassCntl = in kv_populate_vce_table()
1000 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
1002 pi->vce_level_count++; in kv_populate_vce_table()
1006 pi->dpm_table_start + in kv_populate_vce_table()
1008 (u8 *)&pi->vce_level_count, in kv_populate_vce_table()
1010 pi->sram_end); in kv_populate_vce_table()
1014 pi->vce_interval = 1; in kv_populate_vce_table()
1017 pi->dpm_table_start + in kv_populate_vce_table()
1019 (u8 *)&pi->vce_interval, in kv_populate_vce_table()
1021 pi->sram_end); in kv_populate_vce_table()
1026 pi->dpm_table_start + in kv_populate_vce_table()
1028 (u8 *)&pi->vce_level, in kv_populate_vce_table()
1030 pi->sram_end); in kv_populate_vce_table()
1037 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_samu_table() local
1047 pi->samu_level_count = 0; in kv_populate_samu_table()
1049 if (pi->high_voltage_t && in kv_populate_samu_table()
1050 pi->high_voltage_t < table->entries[i].v) in kv_populate_samu_table()
1053 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_samu_table()
1054 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_samu_table()
1056 pi->samu_level[i].ClkBypassCntl = in kv_populate_samu_table()
1063 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
1065 pi->samu_level_count++; in kv_populate_samu_table()
1069 pi->dpm_table_start + in kv_populate_samu_table()
1071 (u8 *)&pi->samu_level_count, in kv_populate_samu_table()
1073 pi->sram_end); in kv_populate_samu_table()
1077 pi->samu_interval = 1; in kv_populate_samu_table()
1080 pi->dpm_table_start + in kv_populate_samu_table()
1082 (u8 *)&pi->samu_interval, in kv_populate_samu_table()
1084 pi->sram_end); in kv_populate_samu_table()
1089 pi->dpm_table_start + in kv_populate_samu_table()
1091 (u8 *)&pi->samu_level, in kv_populate_samu_table()
1093 pi->sram_end); in kv_populate_samu_table()
1103 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_acp_table() local
1113 pi->acp_level_count = 0; in kv_populate_acp_table()
1115 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_acp_table()
1116 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_acp_table()
1122 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
1124 pi->acp_level_count++; in kv_populate_acp_table()
1128 pi->dpm_table_start + in kv_populate_acp_table()
1130 (u8 *)&pi->acp_level_count, in kv_populate_acp_table()
1132 pi->sram_end); in kv_populate_acp_table()
1136 pi->acp_interval = 1; in kv_populate_acp_table()
1139 pi->dpm_table_start + in kv_populate_acp_table()
1141 (u8 *)&pi->acp_interval, in kv_populate_acp_table()
1143 pi->sram_end); in kv_populate_acp_table()
1148 pi->dpm_table_start + in kv_populate_acp_table()
1150 (u8 *)&pi->acp_level, in kv_populate_acp_table()
1152 pi->sram_end); in kv_populate_acp_table()
1161 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dfs_bypass_settings() local
1167 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1168 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1170 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1172 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1174 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1176 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1178 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1180 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1182 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1187 &pi->sys_info.sclk_voltage_mapping_table; in kv_calculate_dfs_bypass_settings()
1188 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
1189 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
1191 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
1193 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
1195 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
1197 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
1199 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
1201 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1203 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
1217 struct kv_power_info *pi = kv_get_pi(adev); in kv_reset_acp_boot_level() local
1219 pi->acp_boot_level = 0xff; in kv_reset_acp_boot_level()
1226 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_current_ps() local
1228 pi->current_rps = *rps; in kv_update_current_ps()
1229 pi->current_ps = *new_ps; in kv_update_current_ps()
1230 pi->current_rps.ps_priv = &pi->current_ps; in kv_update_current_ps()
1231 adev->pm.dpm.current_ps = &pi->current_rps; in kv_update_current_ps()
1238 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_requested_ps() local
1240 pi->requested_rps = *rps; in kv_update_requested_ps()
1241 pi->requested_ps = *new_ps; in kv_update_requested_ps()
1242 pi->requested_rps.ps_priv = &pi->requested_ps; in kv_update_requested_ps()
1243 adev->pm.dpm.requested_ps = &pi->requested_rps; in kv_update_requested_ps()
1249 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable_bapm() local
1252 if (pi->bapm_enable) { in kv_dpm_enable_bapm()
1261 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable() local
1307 if (pi->enable_auto_thermal_throttling) { in kv_dpm_enable()
1372 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_disable() local
1387 if (pi->caps_vce_pg) /* power on the VCE block */ in kv_dpm_disable()
1389 if (pi->caps_uvd_pg) /* power on the UVD block */ in kv_dpm_disable()
1406 struct kv_power_info *pi = kv_get_pi(adev);
1408 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1409 (u8 *)&value, sizeof(u16), pi->sram_end);
1415 struct kv_power_info *pi = kv_get_pi(adev);
1417 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1418 value, pi->sram_end);
1424 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_sclk_t() local
1426 pi->low_sclk_interrupt_t = 0; in kv_init_sclk_t()
1431 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_fps_limits() local
1434 if (pi->caps_fps) { in kv_init_fps_limits()
1438 pi->fps_high_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1440 pi->dpm_table_start + in kv_init_fps_limits()
1442 (u8 *)&pi->fps_high_t, in kv_init_fps_limits()
1443 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1446 pi->fps_low_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1449 pi->dpm_table_start + in kv_init_fps_limits()
1451 (u8 *)&pi->fps_low_t, in kv_init_fps_limits()
1452 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1460 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_powergate_state() local
1462 pi->uvd_power_gated = false; in kv_init_powergate_state()
1463 pi->vce_power_gated = false; in kv_init_powergate_state()
1464 pi->samu_power_gated = false; in kv_init_powergate_state()
1465 pi->acp_power_gated = false; in kv_init_powergate_state()
1495 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_uvd_dpm() local
1503 pi->uvd_boot_level = table->count - 1; in kv_update_uvd_dpm()
1505 pi->uvd_boot_level = 0; in kv_update_uvd_dpm()
1507 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { in kv_update_uvd_dpm()
1508 mask = 1 << pi->uvd_boot_level; in kv_update_uvd_dpm()
1514 pi->dpm_table_start + in kv_update_uvd_dpm()
1516 (uint8_t *)&pi->uvd_boot_level, in kv_update_uvd_dpm()
1517 sizeof(u8), pi->sram_end); in kv_update_uvd_dpm()
1547 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_vce_dpm() local
1553 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1554 pi->vce_boot_level = table->count - 1; in kv_update_vce_dpm()
1556 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); in kv_update_vce_dpm()
1559 pi->dpm_table_start + in kv_update_vce_dpm()
1561 (u8 *)&pi->vce_boot_level, in kv_update_vce_dpm()
1563 pi->sram_end); in kv_update_vce_dpm()
1567 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1570 (1 << pi->vce_boot_level)); in kv_update_vce_dpm()
1581 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_samu_dpm() local
1587 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1588 pi->samu_boot_level = table->count - 1; in kv_update_samu_dpm()
1590 pi->samu_boot_level = 0; in kv_update_samu_dpm()
1593 pi->dpm_table_start + in kv_update_samu_dpm()
1595 (u8 *)&pi->samu_boot_level, in kv_update_samu_dpm()
1597 pi->sram_end); in kv_update_samu_dpm()
1601 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1604 (1 << pi->samu_boot_level)); in kv_update_samu_dpm()
1629 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_boot_level() local
1632 if (!pi->caps_stable_p_state) { in kv_update_acp_boot_level()
1634 if (acp_boot_level != pi->acp_boot_level) { in kv_update_acp_boot_level()
1635 pi->acp_boot_level = acp_boot_level; in kv_update_acp_boot_level()
1638 (1 << pi->acp_boot_level)); in kv_update_acp_boot_level()
1645 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_dpm() local
1651 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1652 pi->acp_boot_level = table->count - 1; in kv_update_acp_dpm()
1654 pi->acp_boot_level = kv_get_acp_boot_level(adev); in kv_update_acp_dpm()
1657 pi->dpm_table_start + in kv_update_acp_dpm()
1659 (u8 *)&pi->acp_boot_level, in kv_update_acp_dpm()
1661 pi->sram_end); in kv_update_acp_dpm()
1665 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1668 (1 << pi->acp_boot_level)); in kv_update_acp_dpm()
1677 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_uvd() local
1680 pi->uvd_power_gated = gate; in kv_dpm_powergate_uvd()
1687 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1691 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1705 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_vce() local
1708 pi->vce_power_gated = gate; in kv_dpm_powergate_vce()
1715 if (pi->caps_vce_pg) /* power off the VCE block */ in kv_dpm_powergate_vce()
1718 if (pi->caps_vce_pg) /* power on the VCE block */ in kv_dpm_powergate_vce()
1730 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_samu() local
1732 if (pi->samu_power_gated == gate) in kv_dpm_powergate_samu()
1735 pi->samu_power_gated = gate; in kv_dpm_powergate_samu()
1739 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1742 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1750 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_acp() local
1752 if (pi->acp_power_gated == gate) in kv_dpm_powergate_acp()
1758 pi->acp_power_gated = gate; in kv_dpm_powergate_acp()
1762 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1765 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1775 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_valid_clock_range() local
1781 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1783 (i == (pi->graphics_dpm_level_count - 1))) { in kv_set_valid_clock_range()
1784 pi->lowest_valid = i; in kv_set_valid_clock_range()
1789 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1793 pi->highest_valid = i; in kv_set_valid_clock_range()
1795 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1796 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1797 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1798 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1800 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1804 &pi->sys_info.sclk_voltage_mapping_table; in kv_set_valid_clock_range()
1806 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1808 i == (int)(pi->graphics_dpm_level_count - 1)) { in kv_set_valid_clock_range()
1809 pi->lowest_valid = i; in kv_set_valid_clock_range()
1814 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1819 pi->highest_valid = i; in kv_set_valid_clock_range()
1821 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1823 table->entries[pi->highest_valid].sclk_frequency) > in kv_set_valid_clock_range()
1824 (table->entries[pi->lowest_valid].sclk_frequency - in kv_set_valid_clock_range()
1826 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1828 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1837 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_dfs_bypass_settings() local
1841 if (pi->caps_enable_dfs_bypass) { in kv_update_dfs_bypass_settings()
1843 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; in kv_update_dfs_bypass_settings()
1845 (pi->dpm_table_start + in kv_update_dfs_bypass_settings()
1847 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + in kv_update_dfs_bypass_settings()
1850 sizeof(u8), pi->sram_end); in kv_update_dfs_bypass_settings()
1859 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_nb_dpm() local
1863 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1866 pi->nb_dpm_enabled = true; in kv_enable_nb_dpm()
1869 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1872 pi->nb_dpm_enabled = false; in kv_enable_nb_dpm()
1907 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_pre_set_power_state() local
1914 &pi->requested_rps, in kv_dpm_pre_set_power_state()
1915 &pi->current_rps); in kv_dpm_pre_set_power_state()
1923 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_set_power_state() local
1924 struct amdgpu_ps *new_ps = &pi->requested_rps; in kv_dpm_set_power_state()
1925 struct amdgpu_ps *old_ps = &pi->current_rps; in kv_dpm_set_power_state()
1928 if (pi->bapm_enable) { in kv_dpm_set_power_state()
1937 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1966 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1998 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_post_set_power_state() local
1999 struct amdgpu_ps *new_ps = &pi->requested_rps; in kv_dpm_post_set_power_state()
2014 struct kv_power_info *pi = kv_get_pi(adev);
2029 kv_set_enabled_level(adev, pi->graphics_boot_level);
2037 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_max_power_limits_table() local
2039 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { in kv_construct_max_power_limits_table()
2040 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; in kv_construct_max_power_limits_table()
2042 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; in kv_construct_max_power_limits_table()
2045 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); in kv_construct_max_power_limits_table()
2048 table->mclk = pi->sys_info.nbp_memory_clock[0]; in kv_construct_max_power_limits_table()
2095 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_boot_state() local
2097 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in kv_construct_boot_state()
2098 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; in kv_construct_boot_state()
2099 pi->boot_pl.ds_divider_index = 0; in kv_construct_boot_state()
2100 pi->boot_pl.ss_divider_index = 0; in kv_construct_boot_state()
2101 pi->boot_pl.allow_gnb_slow = 1; in kv_construct_boot_state()
2102 pi->boot_pl.force_nbp_state = 0; in kv_construct_boot_state()
2103 pi->boot_pl.display_wm = 0; in kv_construct_boot_state()
2104 pi->boot_pl.vce_wm = 0; in kv_construct_boot_state()
2150 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_sleep_divider_id_from_clock() local
2158 if (!pi->caps_sclk_ds) in kv_get_sleep_divider_id_from_clock()
2172 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_high_voltage_limit() local
2179 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2181 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2188 &pi->sys_info.sclk_voltage_mapping_table; in kv_get_high_voltage_limit()
2191 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
2193 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
2209 struct kv_power_info *pi = kv_get_pi(adev); in kv_apply_state_adjust_rules() local
2231 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2261 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2262 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2270 &pi->sys_info.sclk_voltage_mapping_table; in kv_apply_state_adjust_rules()
2273 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2274 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2282 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2288 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2293 pi->battery_state = true; in kv_apply_state_adjust_rules()
2295 pi->battery_state = false; in kv_apply_state_adjust_rules()
2308 if (pi->sys_info.nb_dpm_enable) { in kv_apply_state_adjust_rules()
2309 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_apply_state_adjust_rules()
2310 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2311 pi->disable_nb_ps3_in_battery; in kv_apply_state_adjust_rules()
2323 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enabled_for_throttle() local
2325 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; in kv_dpm_power_level_enabled_for_throttle()
2330 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_ds_divider() local
2334 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_ds_divider()
2337 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_ds_divider()
2338 pi->graphics_level[i].DeepSleepDivId = in kv_calculate_ds_divider()
2340 be32_to_cpu(pi->graphics_level[i].SclkFrequency), in kv_calculate_ds_divider()
2348 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_nbps_level_settings() local
2355 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_nbps_level_settings()
2359 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2360 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2361 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2362 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2365 if (!pi->sys_info.nb_dpm_enable) in kv_calculate_nbps_level_settings()
2368 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_calculate_nbps_level_settings()
2369 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2372 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_nbps_level_settings()
2373 pi->graphics_level[i].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2375 if (pi->battery_state) in kv_calculate_nbps_level_settings()
2376 pi->graphics_level[0].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2378 pi->graphics_level[1].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2379 pi->graphics_level[2].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2380 pi->graphics_level[3].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2381 pi->graphics_level[4].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2384 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2385 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2386 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2387 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2390 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { in kv_calculate_nbps_level_settings()
2391 pi->graphics_level[pi->lowest_valid].UpH = 0x28; in kv_calculate_nbps_level_settings()
2392 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2393 if (pi->lowest_valid != pi->highest_valid) in kv_calculate_nbps_level_settings()
2394 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2402 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dpm_settings() local
2405 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_dpm_settings()
2408 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_dpm_settings()
2409 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; in kv_calculate_dpm_settings()
2416 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_graphics_levels() local
2424 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2426 if (pi->high_voltage_t && in kv_init_graphics_levels()
2427 (pi->high_voltage_t < in kv_init_graphics_levels()
2433 &pi->sys_info.vid_mapping_table, in kv_init_graphics_levels()
2436 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2438 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2442 &pi->sys_info.sclk_voltage_mapping_table; in kv_init_graphics_levels()
2444 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2446 if (pi->high_voltage_t && in kv_init_graphics_levels()
2447 pi->high_voltage_t < in kv_init_graphics_levels()
2453 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2455 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2465 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_new_levels() local
2469 if (i >= pi->lowest_valid && i <= pi->highest_valid) in kv_enable_new_levels()
2485 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_enabled_levels() local
2488 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_set_enabled_levels()
2500 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_nbps_index_settings() local
2506 if (pi->sys_info.nb_dpm_enable) { in kv_program_nbps_index_settings()
2560 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_sys_info_table() local
2577 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); in kv_parse_sys_info_table()
2578 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); in kv_parse_sys_info_table()
2579 pi->sys_info.bootup_nb_voltage_index = in kv_parse_sys_info_table()
2582 pi->sys_info.htc_tmp_lmt = 203; in kv_parse_sys_info_table()
2584 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; in kv_parse_sys_info_table()
2586 pi->sys_info.htc_hyst_lmt = 5; in kv_parse_sys_info_table()
2588 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; in kv_parse_sys_info_table()
2589 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { in kv_parse_sys_info_table()
2594 pi->sys_info.nb_dpm_enable = true; in kv_parse_sys_info_table()
2596 pi->sys_info.nb_dpm_enable = false; in kv_parse_sys_info_table()
2599 pi->sys_info.nbp_memory_clock[i] = in kv_parse_sys_info_table()
2601 pi->sys_info.nbp_n_clock[i] = in kv_parse_sys_info_table()
2606 pi->caps_enable_dfs_bypass = true; in kv_parse_sys_info_table()
2609 &pi->sys_info.sclk_voltage_mapping_table, in kv_parse_sys_info_table()
2613 &pi->sys_info.vid_mapping_table, in kv_parse_sys_info_table()
2646 struct kv_power_info *pi = kv_get_pi(adev); in kv_patch_boot_state() local
2649 ps->levels[0] = pi->boot_pl; in kv_patch_boot_state()
2683 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_pplib_clock_info() local
2695 if (pi->caps_sclk_ds) { in kv_parse_pplib_clock_info()
2793 struct kv_power_info *pi; in kv_dpm_init() local
2796 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); in kv_dpm_init()
2797 if (pi == NULL) in kv_dpm_init()
2799 adev->pm.dpm.priv = pi; in kv_dpm_init()
2810 pi->at[i] = TRINITY_AT_DFLT; in kv_dpm_init()
2812 pi->sram_end = SMC_RAM_END; in kv_dpm_init()
2814 pi->enable_nb_dpm = true; in kv_dpm_init()
2816 pi->caps_power_containment = true; in kv_dpm_init()
2817 pi->caps_cac = true; in kv_dpm_init()
2818 pi->enable_didt = false; in kv_dpm_init()
2819 if (pi->enable_didt) { in kv_dpm_init()
2820 pi->caps_sq_ramping = true; in kv_dpm_init()
2821 pi->caps_db_ramping = true; in kv_dpm_init()
2822 pi->caps_td_ramping = true; in kv_dpm_init()
2823 pi->caps_tcp_ramping = true; in kv_dpm_init()
2827 pi->caps_sclk_ds = true; in kv_dpm_init()
2829 pi->caps_sclk_ds = false; in kv_dpm_init()
2831 pi->enable_auto_thermal_throttling = true; in kv_dpm_init()
2832 pi->disable_nb_ps3_in_battery = false; in kv_dpm_init()
2834 pi->bapm_enable = false; in kv_dpm_init()
2836 pi->bapm_enable = true; in kv_dpm_init()
2837 pi->voltage_drop_t = 0; in kv_dpm_init()
2838 pi->caps_sclk_throttle_low_notification = false; in kv_dpm_init()
2839 pi->caps_fps = false; /* true? */ in kv_dpm_init()
2840 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false; in kv_dpm_init()
2841 pi->caps_uvd_dpm = true; in kv_dpm_init()
2842 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false; in kv_dpm_init()
2843 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false; in kv_dpm_init()
2844 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false; in kv_dpm_init()
2845 pi->caps_stable_p_state = false; in kv_dpm_init()
2858 pi->enable_dpm = true; in kv_dpm_init()
2868 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_debugfs_print_current_performance_level() local
2879 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_debugfs_print_current_performance_level()
2884 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2885 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2931 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_sclk() local
2932 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); in kv_dpm_get_sclk()
2943 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_mclk() local
2945 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_mclk()
3284 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_read_sensor() local
3299 pi->graphics_level[pl_index].SclkFrequency); in kv_dpm_read_sensor()