Lines Matching refs:vmid
381 entry->src_id, entry->ring_id, entry->vmid, in gmc_v9_0_process_interrupt()
432 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, in gmc_v9_0_get_invalidate_req() argument
438 PER_VMID_INVALIDATE_REQ, 1 << vmid); in gmc_v9_0_get_invalidate_req()
467 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, in gmc_v9_0_flush_gpu_tlb() argument
477 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); in gmc_v9_0_flush_gpu_tlb()
489 1 << vmid); in gmc_v9_0_flush_gpu_tlb()
505 if (tmp & (1 << vmid)) in gmc_v9_0_flush_gpu_tlb()
517 unsigned vmid, uint64_t pd_addr) in gmc_v9_0_emit_flush_gpu_tlb() argument
521 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); in gmc_v9_0_emit_flush_gpu_tlb()
524 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), in gmc_v9_0_emit_flush_gpu_tlb()
527 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), in gmc_v9_0_emit_flush_gpu_tlb()
532 req, 1 << vmid); in gmc_v9_0_emit_flush_gpu_tlb()
537 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, in gmc_v9_0_emit_pasid_mapping() argument
548 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; in gmc_v9_0_emit_pasid_mapping()
550 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; in gmc_v9_0_emit_pasid_mapping()