Lines Matching refs:tmp
199 u32 tmp; in gmc_v8_0_mc_resume() local
202 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); in gmc_v8_0_mc_resume()
203 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); in gmc_v8_0_mc_resume()
204 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); in gmc_v8_0_mc_resume()
206 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); in gmc_v8_0_mc_resume()
207 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); in gmc_v8_0_mc_resume()
208 WREG32(mmBIF_FB_EN, tmp); in gmc_v8_0_mc_resume()
453 u32 tmp; in gmc_v8_0_mc_program() local
471 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v8_0_mc_program()
472 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v8_0_mc_program()
473 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v8_0_mc_program()
476 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v8_0_mc_program()
477 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); in gmc_v8_0_mc_program()
478 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v8_0_mc_program()
489 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; in gmc_v8_0_mc_program()
490 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); in gmc_v8_0_mc_program()
491 WREG32(mmMC_VM_FB_LOCATION, tmp); in gmc_v8_0_mc_program()
507 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v8_0_mc_program()
508 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); in gmc_v8_0_mc_program()
509 WREG32(mmHDP_MISC_CNTL, tmp); in gmc_v8_0_mc_program()
511 tmp = RREG32(mmHDP_HOST_PATH_CNTL); in gmc_v8_0_mc_program()
512 WREG32(mmHDP_HOST_PATH_CNTL, tmp); in gmc_v8_0_mc_program()
530 u32 tmp; in gmc_v8_0_mc_init() local
534 tmp = RREG32(mmMC_ARB_RAMCFG); in gmc_v8_0_mc_init()
535 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v8_0_mc_init()
540 tmp = RREG32(mmMC_SHARED_CHMAP); in gmc_v8_0_mc_init()
541 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v8_0_mc_init()
721 u32 tmp; in gmc_v8_0_set_fault_enable_default() local
723 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_set_fault_enable_default()
724 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
726 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
728 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
730 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
732 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
734 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
736 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, in gmc_v8_0_set_fault_enable_default()
738 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_set_fault_enable_default()
749 u32 tmp; in gmc_v8_0_set_prt() local
756 tmp = RREG32(mmVM_PRT_CNTL); in gmc_v8_0_set_prt()
757 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
759 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
761 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
763 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
765 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
767 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
769 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, in gmc_v8_0_set_prt()
771 WREG32(mmVM_PRT_CNTL, tmp); in gmc_v8_0_set_prt()
813 u32 tmp, field; in gmc_v8_0_gart_enable() local
826 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v8_0_gart_enable()
827 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v8_0_gart_enable()
828 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); in gmc_v8_0_gart_enable()
829 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); in gmc_v8_0_gart_enable()
830 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); in gmc_v8_0_gart_enable()
831 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); in gmc_v8_0_gart_enable()
832 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v8_0_gart_enable()
834 tmp = RREG32(mmVM_L2_CNTL); in gmc_v8_0_gart_enable()
835 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
836 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gmc_v8_0_gart_enable()
837 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
838 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
839 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); in gmc_v8_0_gart_enable()
840 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gmc_v8_0_gart_enable()
841 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); in gmc_v8_0_gart_enable()
842 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_enable()
843 tmp = RREG32(mmVM_L2_CNTL2); in gmc_v8_0_gart_enable()
844 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v8_0_gart_enable()
845 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
846 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v8_0_gart_enable()
849 tmp = RREG32(mmVM_L2_CNTL3); in gmc_v8_0_gart_enable()
850 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); in gmc_v8_0_gart_enable()
851 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v8_0_gart_enable()
852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); in gmc_v8_0_gart_enable()
853 WREG32(mmVM_L2_CNTL3, tmp); in gmc_v8_0_gart_enable()
855 tmp = RREG32(mmVM_L2_CNTL4); in gmc_v8_0_gart_enable()
856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
857 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
858 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
859 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
863 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
864 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
865 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); in gmc_v8_0_gart_enable()
866 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); in gmc_v8_0_gart_enable()
867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); in gmc_v8_0_gart_enable()
868 WREG32(mmVM_L2_CNTL4, tmp); in gmc_v8_0_gart_enable()
876 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_gart_enable()
877 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
878 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); in gmc_v8_0_gart_enable()
879 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
880 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_gart_enable()
906 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_gart_enable()
907 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
908 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); in gmc_v8_0_gart_enable()
909 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
910 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
911 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
912 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
913 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
914 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
915 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); in gmc_v8_0_gart_enable()
916 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, in gmc_v8_0_gart_enable()
918 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_gart_enable()
958 u32 tmp; in gmc_v8_0_gart_disable() local
964 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); in gmc_v8_0_gart_disable()
965 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v8_0_gart_disable()
966 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); in gmc_v8_0_gart_disable()
967 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); in gmc_v8_0_gart_disable()
968 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); in gmc_v8_0_gart_disable()
970 tmp = RREG32(mmVM_L2_CNTL); in gmc_v8_0_gart_disable()
971 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v8_0_gart_disable()
972 WREG32(mmVM_L2_CNTL, tmp); in gmc_v8_0_gart_disable()
1089 u32 tmp; in gmc_v8_0_sw_init() local
1093 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); in gmc_v8_0_sw_init()
1095 tmp = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_sw_init()
1096 tmp &= MC_SEQ_MISC0__MT__MASK; in gmc_v8_0_sw_init()
1097 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); in gmc_v8_0_sw_init()
1159 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); in gmc_v8_0_sw_init() local
1161 tmp <<= 22; in gmc_v8_0_sw_init()
1162 adev->vm_manager.vram_base_offset = tmp; in gmc_v8_0_sw_init()
1260 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v8_0_is_idle() local
1262 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | in gmc_v8_0_is_idle()
1272 u32 tmp; in gmc_v8_0_wait_for_idle() local
1277 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | in gmc_v8_0_wait_for_idle()
1283 if (!tmp) in gmc_v8_0_wait_for_idle()
1295 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v8_0_check_soft_reset() local
1297 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) in gmc_v8_0_check_soft_reset()
1301 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | in gmc_v8_0_check_soft_reset()
1341 u32 tmp; in gmc_v8_0_soft_reset() local
1343 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset()
1344 tmp |= srbm_soft_reset; in gmc_v8_0_soft_reset()
1345 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in gmc_v8_0_soft_reset()
1346 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset()
1347 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset()
1351 tmp &= ~srbm_soft_reset; in gmc_v8_0_soft_reset()
1352 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset()
1353 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset()
1378 u32 tmp; in gmc_v8_0_vm_fault_interrupt_state() local
1390 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1391 tmp &= ~bits; in gmc_v8_0_vm_fault_interrupt_state()
1392 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1394 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1395 tmp &= ~bits; in gmc_v8_0_vm_fault_interrupt_state()
1396 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1400 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1401 tmp |= bits; in gmc_v8_0_vm_fault_interrupt_state()
1402 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1404 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1405 tmp |= bits; in gmc_v8_0_vm_fault_interrupt_state()
1406 WREG32(mmVM_CONTEXT1_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()