111 	u32 tmp;  in gmc_v7_0_mc_resume()  local
114 	tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);  in gmc_v7_0_mc_resume()
115 	tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);  in gmc_v7_0_mc_resume()
116 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);  in gmc_v7_0_mc_resume()
118 	tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);  in gmc_v7_0_mc_resume()
119 	tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);  in gmc_v7_0_mc_resume()
120 	WREG32(mmBIF_FB_EN, tmp);  in gmc_v7_0_mc_resume()
262 	u32 tmp;  in gmc_v7_0_mc_program()  local
280 		tmp = RREG32(mmVGA_HDP_CONTROL);  in gmc_v7_0_mc_program()
281 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);  in gmc_v7_0_mc_program()
282 		WREG32(mmVGA_HDP_CONTROL, tmp);  in gmc_v7_0_mc_program()
285 		tmp = RREG32(mmVGA_RENDER_CONTROL);  in gmc_v7_0_mc_program()
286 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);  in gmc_v7_0_mc_program()
287 		WREG32(mmVGA_RENDER_CONTROL, tmp);  in gmc_v7_0_mc_program()
305 	tmp = RREG32(mmHDP_MISC_CNTL);  in gmc_v7_0_mc_program()
306 	tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);  in gmc_v7_0_mc_program()
307 	WREG32(mmHDP_MISC_CNTL, tmp);  in gmc_v7_0_mc_program()
309 	tmp = RREG32(mmHDP_HOST_PATH_CNTL);  in gmc_v7_0_mc_program()
310 	WREG32(mmHDP_HOST_PATH_CNTL, tmp);  in gmc_v7_0_mc_program()
328 		u32 tmp;  in gmc_v7_0_mc_init()  local
332 		tmp = RREG32(mmMC_ARB_RAMCFG);  in gmc_v7_0_mc_init()
333 		if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {  in gmc_v7_0_mc_init()
338 		tmp = RREG32(mmMC_SHARED_CHMAP);  in gmc_v7_0_mc_init()
339 		switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {  in gmc_v7_0_mc_init()
496 	u32 tmp;  in gmc_v7_0_set_fault_enable_default()  local
498 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_set_fault_enable_default()
499 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
501 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
503 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
505 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
507 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
509 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
511 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_set_fault_enable_default()
522 	uint32_t tmp;  in gmc_v7_0_set_prt()  local
529 	tmp = RREG32(mmVM_PRT_CNTL);  in gmc_v7_0_set_prt()
530 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
532 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
534 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
536 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
538 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
540 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
542 	tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,  in gmc_v7_0_set_prt()
544 	WREG32(mmVM_PRT_CNTL, tmp);  in gmc_v7_0_set_prt()
586 	u32 tmp, field;  in gmc_v7_0_gart_enable()  local
599 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_enable()
600 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gmc_v7_0_gart_enable()
601 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);  in gmc_v7_0_gart_enable()
602 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gmc_v7_0_gart_enable()
603 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);  in gmc_v7_0_gart_enable()
604 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);  in gmc_v7_0_gart_enable()
605 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v7_0_gart_enable()
607 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_enable()
608 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gmc_v7_0_gart_enable()
609 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);  in gmc_v7_0_gart_enable()
610 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);  in gmc_v7_0_gart_enable()
611 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);  in gmc_v7_0_gart_enable()
612 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);  in gmc_v7_0_gart_enable()
613 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gmc_v7_0_gart_enable()
614 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);  in gmc_v7_0_gart_enable()
615 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v7_0_gart_enable()
616 	tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gmc_v7_0_gart_enable()
617 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gmc_v7_0_gart_enable()
618 	WREG32(mmVM_L2_CNTL2, tmp);  in gmc_v7_0_gart_enable()
621 	tmp = RREG32(mmVM_L2_CNTL3);  in gmc_v7_0_gart_enable()
622 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);  in gmc_v7_0_gart_enable()
623 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);  in gmc_v7_0_gart_enable()
624 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);  in gmc_v7_0_gart_enable()
625 	WREG32(mmVM_L2_CNTL3, tmp);  in gmc_v7_0_gart_enable()
633 	tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_gart_enable()
634 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gmc_v7_0_gart_enable()
635 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);  in gmc_v7_0_gart_enable()
636 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);  in gmc_v7_0_gart_enable()
637 	WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_gart_enable()
663 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_gart_enable()
664 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gmc_v7_0_gart_enable()
665 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);  in gmc_v7_0_gart_enable()
666 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,  in gmc_v7_0_gart_enable()
668 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_gart_enable()
675 		tmp = RREG32(mmCHUB_CONTROL);  in gmc_v7_0_gart_enable()
676 		tmp &= ~BYPASS_VM;  in gmc_v7_0_gart_enable()
677 		WREG32(mmCHUB_CONTROL, tmp);  in gmc_v7_0_gart_enable()
714 	u32 tmp;  in gmc_v7_0_gart_disable()  local
720 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_disable()
721 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gmc_v7_0_gart_disable()
722 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);  in gmc_v7_0_gart_disable()
723 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);  in gmc_v7_0_gart_disable()
724 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v7_0_gart_disable()
726 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_disable()
727 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);  in gmc_v7_0_gart_disable()
728 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v7_0_gart_disable()
969 		u32 tmp = RREG32(mmMC_SEQ_MISC0);  in gmc_v7_0_sw_init()  local
970 		tmp &= MC_SEQ_MISC0__MT__MASK;  in gmc_v7_0_sw_init()
971 		adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);  in gmc_v7_0_sw_init()
1033 		u64 tmp = RREG32(mmMC_VM_FB_OFFSET);  in gmc_v7_0_sw_init()  local
1035 		tmp <<= 22;  in gmc_v7_0_sw_init()
1036 		adev->vm_manager.vram_base_offset = tmp;  in gmc_v7_0_sw_init()
1126 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_is_idle()  local
1128 	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |  in gmc_v7_0_is_idle()
1138 	u32 tmp;  in gmc_v7_0_wait_for_idle()  local
1143 		tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |  in gmc_v7_0_wait_for_idle()
1148 		if (!tmp)  in gmc_v7_0_wait_for_idle()
1160 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_soft_reset()  local
1162 	if (tmp & SRBM_STATUS__VMC_BUSY_MASK)  in gmc_v7_0_soft_reset()
1166 	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |  in gmc_v7_0_soft_reset()
1180 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1181 		tmp |= srbm_soft_reset;  in gmc_v7_0_soft_reset()
1182 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in gmc_v7_0_soft_reset()
1183 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v7_0_soft_reset()
1184 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1188 		tmp &= ~srbm_soft_reset;  in gmc_v7_0_soft_reset()
1189 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v7_0_soft_reset()
1190 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1207 	u32 tmp;  in gmc_v7_0_vm_fault_interrupt_state()  local
1218 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1219 		tmp &= ~bits;  in gmc_v7_0_vm_fault_interrupt_state()
1220 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1222 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1223 		tmp &= ~bits;  in gmc_v7_0_vm_fault_interrupt_state()
1224 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1228 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1229 		tmp |= bits;  in gmc_v7_0_vm_fault_interrupt_state()
1230 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1232 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1233 		tmp |= bits;  in gmc_v7_0_vm_fault_interrupt_state()
1234 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()