161 			entry->src_id, entry->ring_id, entry->vmid,  in gmc_v10_0_process_interrupt()
202 static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid,  in gmc_v10_0_get_invalidate_req()  argument
209 			    PER_VMID_INVALIDATE_REQ, 1 << vmid);  in gmc_v10_0_get_invalidate_req()
229 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,  in gmc_v10_0_flush_vm_hub()  argument
233 	u32 tmp = gmc_v10_0_get_invalidate_req(vmid, flush_type);  in gmc_v10_0_flush_vm_hub()
250 		tmp &= 1 << vmid;  in gmc_v10_0_flush_vm_hub()
271 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,  in gmc_v10_0_flush_gpu_tlb()  argument
286 		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);  in gmc_v10_0_flush_gpu_tlb()
296 		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);  in gmc_v10_0_flush_gpu_tlb()
335 					     unsigned vmid, uint64_t pd_addr)  in gmc_v10_0_emit_flush_gpu_tlb()  argument
338 	uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);  in gmc_v10_0_emit_flush_gpu_tlb()
341 	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),  in gmc_v10_0_emit_flush_gpu_tlb()
344 	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),  in gmc_v10_0_emit_flush_gpu_tlb()
349 					    req, 1 << vmid);  in gmc_v10_0_emit_flush_gpu_tlb()
354 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,  in gmc_v10_0_emit_pasid_mapping()  argument
361 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;  in gmc_v10_0_emit_pasid_mapping()
363 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;  in gmc_v10_0_emit_pasid_mapping()