112 	uint32_t tmp;  in gfxhub_v2_0_init_tlb_regs()  local
115 	tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v2_0_init_tlb_regs()
117 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gfxhub_v2_0_init_tlb_regs()
118 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gfxhub_v2_0_init_tlb_regs()
119 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v2_0_init_tlb_regs()
121 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v2_0_init_tlb_regs()
123 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);  in gfxhub_v2_0_init_tlb_regs()
124 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v2_0_init_tlb_regs()
127 	WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v2_0_init_tlb_regs()
132 	uint32_t tmp;  in gfxhub_v2_0_init_cache_regs()  local
135 	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);  in gfxhub_v2_0_init_cache_regs()
136 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gfxhub_v2_0_init_cache_regs()
137 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);  in gfxhub_v2_0_init_cache_regs()
138 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,  in gfxhub_v2_0_init_cache_regs()
141 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,  in gfxhub_v2_0_init_cache_regs()
143 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);  in gfxhub_v2_0_init_cache_regs()
144 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gfxhub_v2_0_init_cache_regs()
145 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);  in gfxhub_v2_0_init_cache_regs()
146 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);  in gfxhub_v2_0_init_cache_regs()
148 	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);  in gfxhub_v2_0_init_cache_regs()
149 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gfxhub_v2_0_init_cache_regs()
150 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gfxhub_v2_0_init_cache_regs()
151 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);  in gfxhub_v2_0_init_cache_regs()
153 	tmp = mmGCVM_L2_CNTL3_DEFAULT;  in gfxhub_v2_0_init_cache_regs()
155 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);  in gfxhub_v2_0_init_cache_regs()
156 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,  in gfxhub_v2_0_init_cache_regs()
159 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);  in gfxhub_v2_0_init_cache_regs()
160 		tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,  in gfxhub_v2_0_init_cache_regs()
163 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);  in gfxhub_v2_0_init_cache_regs()
165 	tmp = mmGCVM_L2_CNTL4_DEFAULT;  in gfxhub_v2_0_init_cache_regs()
166 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);  in gfxhub_v2_0_init_cache_regs()
167 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);  in gfxhub_v2_0_init_cache_regs()
168 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);  in gfxhub_v2_0_init_cache_regs()
173 	uint32_t tmp;  in gfxhub_v2_0_enable_system_domain()  local
175 	tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);  in gfxhub_v2_0_enable_system_domain()
176 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v2_0_enable_system_domain()
177 	tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);  in gfxhub_v2_0_enable_system_domain()
178 	WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);  in gfxhub_v2_0_enable_system_domain()
201 	uint32_t tmp;  in gfxhub_v2_0_setup_vmid_config()  local
204 		tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);  in gfxhub_v2_0_setup_vmid_config()
205 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v2_0_setup_vmid_config()
206 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,  in gfxhub_v2_0_setup_vmid_config()
208 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
210 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
212 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
214 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
216 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
218 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
220 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
222 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
226 		tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,  in gfxhub_v2_0_setup_vmid_config()
229 		WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i, tmp);  in gfxhub_v2_0_setup_vmid_config()
281 	u32 tmp;  in gfxhub_v2_0_gart_disable()  local
289 	tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v2_0_gart_disable()
290 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gfxhub_v2_0_gart_disable()
291 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,  in gfxhub_v2_0_gart_disable()
293 	WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v2_0_gart_disable()
309 	u32 tmp;  in gfxhub_v2_0_set_fault_enable_default()  local
310 	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);  in gfxhub_v2_0_set_fault_enable_default()
311 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
313 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
315 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
317 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
319 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
322 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
324 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
326 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
328 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
330 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
332 	tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
335 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
337 		tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v2_0_set_fault_enable_default()
340 	WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);  in gfxhub_v2_0_set_fault_enable_default()