116 	uint32_t tmp;  in gfxhub_v1_0_init_tlb_regs()  local
119 	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v1_0_init_tlb_regs()
121 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gfxhub_v1_0_init_tlb_regs()
122 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gfxhub_v1_0_init_tlb_regs()
123 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
125 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
127 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);  in gfxhub_v1_0_init_tlb_regs()
128 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,  in gfxhub_v1_0_init_tlb_regs()
130 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);  in gfxhub_v1_0_init_tlb_regs()
132 	WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v1_0_init_tlb_regs()
137 	uint32_t tmp;  in gfxhub_v1_0_init_cache_regs()  local
140 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);  in gfxhub_v1_0_init_cache_regs()
141 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gfxhub_v1_0_init_cache_regs()
142 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);  in gfxhub_v1_0_init_cache_regs()
144 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,  in gfxhub_v1_0_init_cache_regs()
146 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);  in gfxhub_v1_0_init_cache_regs()
147 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gfxhub_v1_0_init_cache_regs()
148 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);  in gfxhub_v1_0_init_cache_regs()
149 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);  in gfxhub_v1_0_init_cache_regs()
151 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);  in gfxhub_v1_0_init_cache_regs()
152 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gfxhub_v1_0_init_cache_regs()
153 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gfxhub_v1_0_init_cache_regs()
154 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);  in gfxhub_v1_0_init_cache_regs()
156 	tmp = mmVM_L2_CNTL3_DEFAULT;  in gfxhub_v1_0_init_cache_regs()
158 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);  in gfxhub_v1_0_init_cache_regs()
159 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,  in gfxhub_v1_0_init_cache_regs()
162 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);  in gfxhub_v1_0_init_cache_regs()
163 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,  in gfxhub_v1_0_init_cache_regs()
166 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);  in gfxhub_v1_0_init_cache_regs()
168 	tmp = mmVM_L2_CNTL4_DEFAULT;  in gfxhub_v1_0_init_cache_regs()
169 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);  in gfxhub_v1_0_init_cache_regs()
170 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);  in gfxhub_v1_0_init_cache_regs()
171 	WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);  in gfxhub_v1_0_init_cache_regs()
176 	uint32_t tmp;  in gfxhub_v1_0_enable_system_domain()  local
178 	tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);  in gfxhub_v1_0_enable_system_domain()
179 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v1_0_enable_system_domain()
180 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);  in gfxhub_v1_0_enable_system_domain()
181 	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);  in gfxhub_v1_0_enable_system_domain()
204 	uint32_t tmp;  in gfxhub_v1_0_setup_vmid_config()  local
215 		tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);  in gfxhub_v1_0_setup_vmid_config()
216 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gfxhub_v1_0_setup_vmid_config()
217 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,  in gfxhub_v1_0_setup_vmid_config()
219 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
221 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
224 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
226 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
228 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
230 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
232 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
234 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
238 		tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gfxhub_v1_0_setup_vmid_config()
241 		WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);  in gfxhub_v1_0_setup_vmid_config()
293 	u32 tmp;  in gfxhub_v1_0_gart_disable()  local
301 	tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);  in gfxhub_v1_0_gart_disable()
302 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gfxhub_v1_0_gart_disable()
303 	tmp = REG_SET_FIELD(tmp,  in gfxhub_v1_0_gart_disable()
307 	WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gfxhub_v1_0_gart_disable()
323 	u32 tmp;  in gfxhub_v1_0_set_fault_enable_default()  local
324 	tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);  in gfxhub_v1_0_set_fault_enable_default()
325 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
327 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
329 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
331 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
333 	tmp = REG_SET_FIELD(tmp,  in gfxhub_v1_0_set_fault_enable_default()
337 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
339 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
341 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
343 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
345 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
347 	tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
350 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
352 		tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,  in gfxhub_v1_0_set_fault_enable_default()
355 	WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);  in gfxhub_v1_0_set_fault_enable_default()