3415 	struct v9_mqd *mqd = ring->mqd_ptr;  in gfx_v9_0_mqd_init()  local
3419 	mqd->header = 0xC0310800;  in gfx_v9_0_mqd_init()
3420 	mqd->compute_pipelinestat_enable = 0x00000001;  in gfx_v9_0_mqd_init()
3421 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;  in gfx_v9_0_mqd_init()
3422 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;  in gfx_v9_0_mqd_init()
3423 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;  in gfx_v9_0_mqd_init()
3424 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;  in gfx_v9_0_mqd_init()
3425 	mqd->compute_static_thread_mgmt_se4 = 0xffffffff;  in gfx_v9_0_mqd_init()
3426 	mqd->compute_static_thread_mgmt_se5 = 0xffffffff;  in gfx_v9_0_mqd_init()
3427 	mqd->compute_static_thread_mgmt_se6 = 0xffffffff;  in gfx_v9_0_mqd_init()
3428 	mqd->compute_static_thread_mgmt_se7 = 0xffffffff;  in gfx_v9_0_mqd_init()
3429 	mqd->compute_misc_reserved = 0x00000003;  in gfx_v9_0_mqd_init()
3431 	mqd->dynamic_cu_mask_addr_lo =  in gfx_v9_0_mqd_init()
3434 	mqd->dynamic_cu_mask_addr_hi =  in gfx_v9_0_mqd_init()
3439 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;  in gfx_v9_0_mqd_init()
3440 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);  in gfx_v9_0_mqd_init()
3447 	mqd->cp_hqd_eop_control = tmp;  in gfx_v9_0_mqd_init()
3466 	mqd->cp_hqd_pq_doorbell_control = tmp;  in gfx_v9_0_mqd_init()
3470 	mqd->cp_hqd_dequeue_request = 0;  in gfx_v9_0_mqd_init()
3471 	mqd->cp_hqd_pq_rptr = 0;  in gfx_v9_0_mqd_init()
3472 	mqd->cp_hqd_pq_wptr_lo = 0;  in gfx_v9_0_mqd_init()
3473 	mqd->cp_hqd_pq_wptr_hi = 0;  in gfx_v9_0_mqd_init()
3476 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;  in gfx_v9_0_mqd_init()
3477 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);  in gfx_v9_0_mqd_init()
3482 	mqd->cp_mqd_control = tmp;  in gfx_v9_0_mqd_init()
3486 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;  in gfx_v9_0_mqd_init()
3487 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);  in gfx_v9_0_mqd_init()
3502 	mqd->cp_hqd_pq_control = tmp;  in gfx_v9_0_mqd_init()
3506 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v9_0_mqd_init()
3507 	mqd->cp_hqd_pq_rptr_report_addr_hi =  in gfx_v9_0_mqd_init()
3512 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v9_0_mqd_init()
3513 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v9_0_mqd_init()
3530 	mqd->cp_hqd_pq_doorbell_control = tmp;  in gfx_v9_0_mqd_init()
3534 	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);  in gfx_v9_0_mqd_init()
3537 	mqd->cp_hqd_vmid = 0;  in gfx_v9_0_mqd_init()
3541 	mqd->cp_hqd_persistent_state = tmp;  in gfx_v9_0_mqd_init()
3546 	mqd->cp_hqd_ib_control = tmp;  in gfx_v9_0_mqd_init()
3549 	mqd->cp_hqd_active = 1;  in gfx_v9_0_mqd_init()
3557 	struct v9_mqd *mqd = ring->mqd_ptr;  in gfx_v9_0_kiq_init_register()  local
3564 	       mqd->cp_hqd_eop_base_addr_lo);  in gfx_v9_0_kiq_init_register()
3566 	       mqd->cp_hqd_eop_base_addr_hi);  in gfx_v9_0_kiq_init_register()
3570 	       mqd->cp_hqd_eop_control);  in gfx_v9_0_kiq_init_register()
3574 	       mqd->cp_hqd_pq_doorbell_control);  in gfx_v9_0_kiq_init_register()
3585 		       mqd->cp_hqd_dequeue_request);  in gfx_v9_0_kiq_init_register()
3587 		       mqd->cp_hqd_pq_rptr);  in gfx_v9_0_kiq_init_register()
3589 		       mqd->cp_hqd_pq_wptr_lo);  in gfx_v9_0_kiq_init_register()
3591 		       mqd->cp_hqd_pq_wptr_hi);  in gfx_v9_0_kiq_init_register()
3596 	       mqd->cp_mqd_base_addr_lo);  in gfx_v9_0_kiq_init_register()
3598 	       mqd->cp_mqd_base_addr_hi);  in gfx_v9_0_kiq_init_register()
3602 	       mqd->cp_mqd_control);  in gfx_v9_0_kiq_init_register()
3606 	       mqd->cp_hqd_pq_base_lo);  in gfx_v9_0_kiq_init_register()
3608 	       mqd->cp_hqd_pq_base_hi);  in gfx_v9_0_kiq_init_register()
3612 	       mqd->cp_hqd_pq_control);  in gfx_v9_0_kiq_init_register()
3616 				mqd->cp_hqd_pq_rptr_report_addr_lo);  in gfx_v9_0_kiq_init_register()
3618 				mqd->cp_hqd_pq_rptr_report_addr_hi);  in gfx_v9_0_kiq_init_register()
3622 	       mqd->cp_hqd_pq_wptr_poll_addr_lo);  in gfx_v9_0_kiq_init_register()
3624 	       mqd->cp_hqd_pq_wptr_poll_addr_hi);  in gfx_v9_0_kiq_init_register()
3635 	       mqd->cp_hqd_pq_doorbell_control);  in gfx_v9_0_kiq_init_register()
3639 	       mqd->cp_hqd_pq_wptr_lo);  in gfx_v9_0_kiq_init_register()
3641 	       mqd->cp_hqd_pq_wptr_hi);  in gfx_v9_0_kiq_init_register()
3644 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);  in gfx_v9_0_kiq_init_register()
3647 	       mqd->cp_hqd_persistent_state);  in gfx_v9_0_kiq_init_register()
3651 	       mqd->cp_hqd_active);  in gfx_v9_0_kiq_init_register()
3701 	struct v9_mqd *mqd = ring->mqd_ptr;  in gfx_v9_0_kiq_init_queue()  local
3709 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));  in gfx_v9_0_kiq_init_queue()
3721 		memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));  in gfx_v9_0_kiq_init_queue()
3722 		((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;  in gfx_v9_0_kiq_init_queue()
3723 		((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;  in gfx_v9_0_kiq_init_queue()
3732 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));  in gfx_v9_0_kiq_init_queue()
3741 	struct v9_mqd *mqd = ring->mqd_ptr;  in gfx_v9_0_kcq_init_queue()  local
3745 		memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));  in gfx_v9_0_kcq_init_queue()
3746 		((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;  in gfx_v9_0_kcq_init_queue()
3747 		((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;  in gfx_v9_0_kcq_init_queue()
3755 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));  in gfx_v9_0_kcq_init_queue()
3759 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));  in gfx_v9_0_kcq_init_queue()