4460 	struct vi_mqd *mqd = ring->mqd_ptr;  in gfx_v8_0_mqd_init()  local
4464 	mqd->header = 0xC0310800;  in gfx_v8_0_mqd_init()
4465 	mqd->compute_pipelinestat_enable = 0x00000001;  in gfx_v8_0_mqd_init()
4466 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;  in gfx_v8_0_mqd_init()
4467 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;  in gfx_v8_0_mqd_init()
4468 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;  in gfx_v8_0_mqd_init()
4469 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;  in gfx_v8_0_mqd_init()
4470 	mqd->compute_misc_reserved = 0x00000003;  in gfx_v8_0_mqd_init()
4471 	mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr  in gfx_v8_0_mqd_init()
4473 	mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr  in gfx_v8_0_mqd_init()
4476 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;  in gfx_v8_0_mqd_init()
4477 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);  in gfx_v8_0_mqd_init()
4484 	mqd->cp_hqd_eop_control = tmp;  in gfx_v8_0_mqd_init()
4492 	mqd->cp_hqd_pq_doorbell_control = tmp;  in gfx_v8_0_mqd_init()
4495 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;  in gfx_v8_0_mqd_init()
4496 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);  in gfx_v8_0_mqd_init()
4501 	mqd->cp_mqd_control = tmp;  in gfx_v8_0_mqd_init()
4505 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;  in gfx_v8_0_mqd_init()
4506 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);  in gfx_v8_0_mqd_init()
4521 	mqd->cp_hqd_pq_control = tmp;  in gfx_v8_0_mqd_init()
4525 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v8_0_mqd_init()
4526 	mqd->cp_hqd_pq_rptr_report_addr_hi =  in gfx_v8_0_mqd_init()
4531 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v8_0_mqd_init()
4532 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v8_0_mqd_init()
4549 	mqd->cp_hqd_pq_doorbell_control = tmp;  in gfx_v8_0_mqd_init()
4553 	mqd->cp_hqd_pq_wptr = ring->wptr;  in gfx_v8_0_mqd_init()
4554 	mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);  in gfx_v8_0_mqd_init()
4557 	mqd->cp_hqd_vmid = 0;  in gfx_v8_0_mqd_init()
4561 	mqd->cp_hqd_persistent_state = tmp;  in gfx_v8_0_mqd_init()
4567 	mqd->cp_hqd_ib_control = tmp;  in gfx_v8_0_mqd_init()
4571 	mqd->cp_hqd_iq_timer = tmp;  in gfx_v8_0_mqd_init()
4575 	mqd->cp_hqd_ctx_save_control = tmp;  in gfx_v8_0_mqd_init()
4578 	mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);  in gfx_v8_0_mqd_init()
4579 	mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);  in gfx_v8_0_mqd_init()
4580 	mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);  in gfx_v8_0_mqd_init()
4581 	mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);  in gfx_v8_0_mqd_init()
4582 	mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);  in gfx_v8_0_mqd_init()
4583 	mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);  in gfx_v8_0_mqd_init()
4584 	mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);  in gfx_v8_0_mqd_init()
4585 	mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);  in gfx_v8_0_mqd_init()
4586 	mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);  in gfx_v8_0_mqd_init()
4587 	mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);  in gfx_v8_0_mqd_init()
4588 	mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);  in gfx_v8_0_mqd_init()
4589 	mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);  in gfx_v8_0_mqd_init()
4590 	mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);  in gfx_v8_0_mqd_init()
4591 	mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);  in gfx_v8_0_mqd_init()
4592 	mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);  in gfx_v8_0_mqd_init()
4595 	mqd->cp_hqd_active = 1;  in gfx_v8_0_mqd_init()
4601 			struct vi_mqd *mqd)  in gfx_v8_0_mqd_commit()  argument
4607 	mqd_data = &mqd->cp_mqd_base_addr_lo;  in gfx_v8_0_mqd_commit()
4622 		WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);  in gfx_v8_0_mqd_commit()
4623 		WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);  in gfx_v8_0_mqd_commit()
4624 		WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);  in gfx_v8_0_mqd_commit()
4640 	struct vi_mqd *mqd = ring->mqd_ptr;  in gfx_v8_0_kiq_init_queue()  local
4648 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kiq_init_queue()
4655 		gfx_v8_0_mqd_commit(adev, mqd);  in gfx_v8_0_kiq_init_queue()
4659 		memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kiq_init_queue()
4660 		((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;  in gfx_v8_0_kiq_init_queue()
4661 		((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;  in gfx_v8_0_kiq_init_queue()
4665 		gfx_v8_0_mqd_commit(adev, mqd);  in gfx_v8_0_kiq_init_queue()
4670 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kiq_init_queue()
4679 	struct vi_mqd *mqd = ring->mqd_ptr;  in gfx_v8_0_kcq_init_queue()  local
4683 		memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kcq_init_queue()
4684 		((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;  in gfx_v8_0_kcq_init_queue()
4685 		((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;  in gfx_v8_0_kcq_init_queue()
4693 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kcq_init_queue()
4697 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));  in gfx_v8_0_kcq_init_queue()