853 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));  in gfx_v8_0_ring_test_ring()
895 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);  in gfx_v8_0_ring_test_ib()
1254 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_get_csb_buffer()
1257 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v8_0_get_csb_buffer()
1265 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));  in gfx_v8_0_get_csb_buffer()
1276 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));  in gfx_v8_0_get_csb_buffer()
1282 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_get_csb_buffer()
1285 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v8_0_get_csb_buffer()
1601 		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1607 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);  in gfx_v8_0_do_edc_gpr_workarounds()
1613 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);  in gfx_v8_0_do_edc_gpr_workarounds()
1621 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1627 		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1633 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);  in gfx_v8_0_do_edc_gpr_workarounds()
1639 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);  in gfx_v8_0_do_edc_gpr_workarounds()
1647 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
1653 		ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);  in gfx_v8_0_do_edc_gpr_workarounds()
1659 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);  in gfx_v8_0_do_edc_gpr_workarounds()
1665 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);  in gfx_v8_0_do_edc_gpr_workarounds()
1673 	ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);  in gfx_v8_0_do_edc_gpr_workarounds()
4215 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_cp_gfx_start()
4218 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v8_0_cp_gfx_start()
4226 				       PACKET3(PACKET3_SET_CONTEXT_REG,  in gfx_v8_0_cp_gfx_start()
4236 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));  in gfx_v8_0_cp_gfx_start()
4241 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v8_0_cp_gfx_start()
4244 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v8_0_cp_gfx_start()
4248 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));  in gfx_v8_0_cp_gfx_start()
4402 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));  in gfx_v8_0_kiq_kcq_enable()
4416 		amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));  in gfx_v8_0_kiq_kcq_enable()
4865 		amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));  in gfx_v8_0_kcq_disable()
5209 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_gds_switch()
5217 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_gds_switch()
5225 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_gds_switch()
5233 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_gds_switch()
6093 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v8_0_ring_emit_hdp_flush()
6106 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in gfx_v8_0_ring_emit_vgt_flush()
6110 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in gfx_v8_0_ring_emit_vgt_flush()
6124 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);  in gfx_v8_0_ring_emit_ib_gfx()
6126 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);  in gfx_v8_0_ring_emit_ib_gfx()
6166 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in gfx_v8_0_ring_emit_ib_compute()
6171 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));  in gfx_v8_0_ring_emit_ib_compute()
6188 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));  in gfx_v8_0_ring_emit_fence_gfx()
6208 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v8_0_ring_emit_pipeline_sync()
6227 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v8_0_ring_emit_vm_flush()
6240 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));  in gfx_v8_0_ring_emit_vm_flush()
6365 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));  in gfx_v8_0_ring_emit_fence_compute()
6385 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_fence_kiq()
6394 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_fence_kiq()
6405 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v8_ring_emit_sb()
6437 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v8_ring_emit_cntxcntl()
6446 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));  in gfx_v8_0_ring_emit_init_cond_exec()
6473 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));  in gfx_v8_0_ring_emit_rreg()
6502 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v8_0_ring_emit_wreg()
6920 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6965 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6995 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
7205 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce));  in gfx_v8_0_ring_emit_ce_meta()
7238 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de));  in gfx_v8_0_ring_emit_de_meta()