2929 			     struct cik_mqd *mqd,  in gfx_v7_0_mqd_init()  argument
2937 	memset(mqd, 0, sizeof(struct cik_mqd));  in gfx_v7_0_mqd_init()
2939 	mqd->header = 0xC0310800;  in gfx_v7_0_mqd_init()
2940 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;  in gfx_v7_0_mqd_init()
2941 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;  in gfx_v7_0_mqd_init()
2942 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;  in gfx_v7_0_mqd_init()
2943 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;  in gfx_v7_0_mqd_init()
2946 	mqd->cp_hqd_pq_doorbell_control =  in gfx_v7_0_mqd_init()
2949 		mqd->cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;  in gfx_v7_0_mqd_init()
2951 		mqd->cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;  in gfx_v7_0_mqd_init()
2954 	mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;  in gfx_v7_0_mqd_init()
2955 	mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);  in gfx_v7_0_mqd_init()
2958 	mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);  in gfx_v7_0_mqd_init()
2959 	mqd->cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;  in gfx_v7_0_mqd_init()
2963 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;  in gfx_v7_0_mqd_init()
2964 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);  in gfx_v7_0_mqd_init()
2967 	mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);  in gfx_v7_0_mqd_init()
2968 	mqd->cp_hqd_pq_control &=  in gfx_v7_0_mqd_init()
2972 	mqd->cp_hqd_pq_control |=  in gfx_v7_0_mqd_init()
2974 	mqd->cp_hqd_pq_control |=  in gfx_v7_0_mqd_init()
2977 	mqd->cp_hqd_pq_control |=  in gfx_v7_0_mqd_init()
2980 	mqd->cp_hqd_pq_control &=  in gfx_v7_0_mqd_init()
2984 	mqd->cp_hqd_pq_control |=  in gfx_v7_0_mqd_init()
2990 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v7_0_mqd_init()
2991 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v7_0_mqd_init()
2995 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v7_0_mqd_init()
2996 	mqd->cp_hqd_pq_rptr_report_addr_hi =  in gfx_v7_0_mqd_init()
3001 		mqd->cp_hqd_pq_doorbell_control =  in gfx_v7_0_mqd_init()
3003 		mqd->cp_hqd_pq_doorbell_control &=  in gfx_v7_0_mqd_init()
3005 		mqd->cp_hqd_pq_doorbell_control |=  in gfx_v7_0_mqd_init()
3008 		mqd->cp_hqd_pq_doorbell_control |=  in gfx_v7_0_mqd_init()
3010 		mqd->cp_hqd_pq_doorbell_control &=  in gfx_v7_0_mqd_init()
3015 		mqd->cp_hqd_pq_doorbell_control = 0;  in gfx_v7_0_mqd_init()
3020 	mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);  in gfx_v7_0_mqd_init()
3021 	mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);  in gfx_v7_0_mqd_init()
3024 	mqd->cp_hqd_vmid = 0;  in gfx_v7_0_mqd_init()
3027 	mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);  in gfx_v7_0_mqd_init()
3028 	mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);  in gfx_v7_0_mqd_init()
3029 	mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);  in gfx_v7_0_mqd_init()
3030 	mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);  in gfx_v7_0_mqd_init()
3031 	mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);  in gfx_v7_0_mqd_init()
3032 	mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);  in gfx_v7_0_mqd_init()
3033 	mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);  in gfx_v7_0_mqd_init()
3034 	mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);  in gfx_v7_0_mqd_init()
3035 	mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);  in gfx_v7_0_mqd_init()
3036 	mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);  in gfx_v7_0_mqd_init()
3037 	mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);  in gfx_v7_0_mqd_init()
3038 	mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);  in gfx_v7_0_mqd_init()
3039 	mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);  in gfx_v7_0_mqd_init()
3040 	mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);  in gfx_v7_0_mqd_init()
3041 	mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);  in gfx_v7_0_mqd_init()
3042 	mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);  in gfx_v7_0_mqd_init()
3045 	mqd->cp_hqd_active = 1;  in gfx_v7_0_mqd_init()
3048 int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)  in gfx_v7_0_mqd_commit()  argument
3055 	mqd_data = &mqd->cp_mqd_base_addr_lo;  in gfx_v7_0_mqd_commit()
3077 	struct cik_mqd *mqd;  in gfx_v7_0_compute_queue_init()  local
3082 				      &mqd_gpu_addr, (void **)&mqd);  in gfx_v7_0_compute_queue_init()
3091 	gfx_v7_0_mqd_init(adev, mqd, mqd_gpu_addr, ring);  in gfx_v7_0_compute_queue_init()
3093 	gfx_v7_0_mqd_commit(adev, mqd);  in gfx_v7_0_compute_queue_init()