2104 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));  in gfx_v7_0_ring_test_ring()
2151 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v7_0_ring_emit_hdp_flush()
2164 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in gfx_v7_0_ring_emit_vgt_flush()
2168 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));  in gfx_v7_0_ring_emit_vgt_flush()
2190 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));  in gfx_v7_0_ring_emit_fence_gfx()
2202 	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));  in gfx_v7_0_ring_emit_fence_gfx()
2231 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));  in gfx_v7_0_ring_emit_fence_compute()
2268 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v7_0_ring_emit_ib_gfx()
2273 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);  in gfx_v7_0_ring_emit_ib_gfx()
2275 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);  in gfx_v7_0_ring_emit_ib_gfx()
2308 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in gfx_v7_0_ring_emit_ib_compute()
2313 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));  in gfx_v7_0_ring_emit_ib_compute()
2338 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v7_ring_emit_cntxcntl()
2371 	ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);  in gfx_v7_0_ring_test_ib()
2544 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));  in gfx_v7_0_cp_gfx_start()
2550 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v7_0_cp_gfx_start()
2553 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v7_0_cp_gfx_start()
2561 						  PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));  in gfx_v7_0_cp_gfx_start()
2569 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));  in gfx_v7_0_cp_gfx_start()
2574 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v7_0_cp_gfx_start()
2577 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v7_0_cp_gfx_start()
2580 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));  in gfx_v7_0_cp_gfx_start()
3217 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v7_0_ring_emit_pipeline_sync()
3229 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v7_0_ring_emit_pipeline_sync()
3231 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v7_0_ring_emit_pipeline_sync()
3258 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));  in gfx_v7_0_ring_emit_vm_flush()
3271 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));  in gfx_v7_0_ring_emit_vm_flush()
3275 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v7_0_ring_emit_vm_flush()
3277 		amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));  in gfx_v7_0_ring_emit_vm_flush()
3287 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v7_0_ring_emit_wreg()
3980 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v7_0_get_csb_buffer()
3983 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));  in gfx_v7_0_get_csb_buffer()
3991 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));  in gfx_v7_0_get_csb_buffer()
4001 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));  in gfx_v7_0_get_csb_buffer()
4027 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in gfx_v7_0_get_csb_buffer()
4030 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));  in gfx_v7_0_get_csb_buffer()
4097 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v7_0_ring_emit_gds_switch()
4105 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v7_0_ring_emit_gds_switch()
4113 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v7_0_ring_emit_gds_switch()
4121 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));  in gfx_v7_0_ring_emit_gds_switch()
5001 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
5033 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),