Lines Matching refs:mqd
2980 struct v10_gfx_mqd *mqd = ring->mqd_ptr; in gfx_v10_0_gfx_mqd_init() local
2986 mqd->cp_gfx_hqd_wptr = 0; in gfx_v10_0_gfx_mqd_init()
2987 mqd->cp_gfx_hqd_wptr_hi = 0; in gfx_v10_0_gfx_mqd_init()
2990 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; in gfx_v10_0_gfx_mqd_init()
2991 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); in gfx_v10_0_gfx_mqd_init()
2998 mqd->cp_gfx_mqd_control = tmp; in gfx_v10_0_gfx_mqd_init()
3003 mqd->cp_gfx_hqd_vmid = 0; in gfx_v10_0_gfx_mqd_init()
3009 mqd->cp_gfx_hqd_queue_priority = tmp; in gfx_v10_0_gfx_mqd_init()
3014 mqd->cp_gfx_hqd_quantum = tmp; in gfx_v10_0_gfx_mqd_init()
3018 mqd->cp_gfx_hqd_base = hqd_gpu_addr; in gfx_v10_0_gfx_mqd_init()
3019 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v10_0_gfx_mqd_init()
3023 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; in gfx_v10_0_gfx_mqd_init()
3024 mqd->cp_gfx_hqd_rptr_addr_hi = in gfx_v10_0_gfx_mqd_init()
3029 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v10_0_gfx_mqd_init()
3030 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v10_0_gfx_mqd_init()
3040 mqd->cp_gfx_hqd_cntl = tmp; in gfx_v10_0_gfx_mqd_init()
3052 mqd->cp_rb_doorbell_control = tmp; in gfx_v10_0_gfx_mqd_init()
3056 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); in gfx_v10_0_gfx_mqd_init()
3059 mqd->cp_gfx_hqd_active = 1; in gfx_v10_0_gfx_mqd_init()
3068 struct v10_gfx_mqd *mqd = ring->mqd_ptr; in gfx_v10_0_gfx_queue_init_register() local
3071 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); in gfx_v10_0_gfx_queue_init_register()
3072 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); in gfx_v10_0_gfx_queue_init_register()
3075 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); in gfx_v10_0_gfx_queue_init_register()
3076 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); in gfx_v10_0_gfx_queue_init_register()
3079 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); in gfx_v10_0_gfx_queue_init_register()
3082 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); in gfx_v10_0_gfx_queue_init_register()
3085 mqd->cp_gfx_hqd_queue_priority); in gfx_v10_0_gfx_queue_init_register()
3086 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); in gfx_v10_0_gfx_queue_init_register()
3089 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); in gfx_v10_0_gfx_queue_init_register()
3090 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); in gfx_v10_0_gfx_queue_init_register()
3093 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); in gfx_v10_0_gfx_queue_init_register()
3094 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); in gfx_v10_0_gfx_queue_init_register()
3097 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); in gfx_v10_0_gfx_queue_init_register()
3100 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); in gfx_v10_0_gfx_queue_init_register()
3101 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); in gfx_v10_0_gfx_queue_init_register()
3104 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); in gfx_v10_0_gfx_queue_init_register()
3107 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); in gfx_v10_0_gfx_queue_init_register()
3116 struct v10_gfx_mqd *mqd = ring->mqd_ptr; in gfx_v10_0_gfx_init_queue() local
3119 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v10_0_gfx_init_queue()
3129 memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], mqd, sizeof(*mqd)); in gfx_v10_0_gfx_init_queue()
3133 memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd)); in gfx_v10_0_gfx_init_queue()
3222 struct v10_compute_mqd *mqd = ring->mqd_ptr; in gfx_v10_0_compute_mqd_init() local
3226 mqd->header = 0xC0310800; in gfx_v10_0_compute_mqd_init()
3227 mqd->compute_pipelinestat_enable = 0x00000001; in gfx_v10_0_compute_mqd_init()
3228 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in gfx_v10_0_compute_mqd_init()
3229 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in gfx_v10_0_compute_mqd_init()
3230 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in gfx_v10_0_compute_mqd_init()
3231 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in gfx_v10_0_compute_mqd_init()
3232 mqd->compute_misc_reserved = 0x00000003; in gfx_v10_0_compute_mqd_init()
3235 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; in gfx_v10_0_compute_mqd_init()
3236 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); in gfx_v10_0_compute_mqd_init()
3243 mqd->cp_hqd_eop_control = tmp; in gfx_v10_0_compute_mqd_init()
3262 mqd->cp_hqd_pq_doorbell_control = tmp; in gfx_v10_0_compute_mqd_init()
3266 mqd->cp_hqd_dequeue_request = 0; in gfx_v10_0_compute_mqd_init()
3267 mqd->cp_hqd_pq_rptr = 0; in gfx_v10_0_compute_mqd_init()
3268 mqd->cp_hqd_pq_wptr_lo = 0; in gfx_v10_0_compute_mqd_init()
3269 mqd->cp_hqd_pq_wptr_hi = 0; in gfx_v10_0_compute_mqd_init()
3272 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; in gfx_v10_0_compute_mqd_init()
3273 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); in gfx_v10_0_compute_mqd_init()
3278 mqd->cp_mqd_control = tmp; in gfx_v10_0_compute_mqd_init()
3282 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; in gfx_v10_0_compute_mqd_init()
3283 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v10_0_compute_mqd_init()
3298 mqd->cp_hqd_pq_control = tmp; in gfx_v10_0_compute_mqd_init()
3302 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v10_0_compute_mqd_init()
3303 mqd->cp_hqd_pq_rptr_report_addr_hi = in gfx_v10_0_compute_mqd_init()
3308 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v10_0_compute_mqd_init()
3309 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v10_0_compute_mqd_init()
3326 mqd->cp_hqd_pq_doorbell_control = tmp; in gfx_v10_0_compute_mqd_init()
3330 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); in gfx_v10_0_compute_mqd_init()
3333 mqd->cp_hqd_vmid = 0; in gfx_v10_0_compute_mqd_init()
3337 mqd->cp_hqd_persistent_state = tmp; in gfx_v10_0_compute_mqd_init()
3342 mqd->cp_hqd_ib_control = tmp; in gfx_v10_0_compute_mqd_init()
3345 mqd->cp_hqd_active = 1; in gfx_v10_0_compute_mqd_init()
3353 struct v10_compute_mqd *mqd = ring->mqd_ptr; in gfx_v10_0_kiq_init_register() local
3361 mqd->cp_hqd_eop_base_addr_lo); in gfx_v10_0_kiq_init_register()
3363 mqd->cp_hqd_eop_base_addr_hi); in gfx_v10_0_kiq_init_register()
3367 mqd->cp_hqd_eop_control); in gfx_v10_0_kiq_init_register()
3371 mqd->cp_hqd_pq_doorbell_control); in gfx_v10_0_kiq_init_register()
3382 mqd->cp_hqd_dequeue_request); in gfx_v10_0_kiq_init_register()
3384 mqd->cp_hqd_pq_rptr); in gfx_v10_0_kiq_init_register()
3386 mqd->cp_hqd_pq_wptr_lo); in gfx_v10_0_kiq_init_register()
3388 mqd->cp_hqd_pq_wptr_hi); in gfx_v10_0_kiq_init_register()
3393 mqd->cp_mqd_base_addr_lo); in gfx_v10_0_kiq_init_register()
3395 mqd->cp_mqd_base_addr_hi); in gfx_v10_0_kiq_init_register()
3399 mqd->cp_mqd_control); in gfx_v10_0_kiq_init_register()
3403 mqd->cp_hqd_pq_base_lo); in gfx_v10_0_kiq_init_register()
3405 mqd->cp_hqd_pq_base_hi); in gfx_v10_0_kiq_init_register()
3409 mqd->cp_hqd_pq_control); in gfx_v10_0_kiq_init_register()
3413 mqd->cp_hqd_pq_rptr_report_addr_lo); in gfx_v10_0_kiq_init_register()
3415 mqd->cp_hqd_pq_rptr_report_addr_hi); in gfx_v10_0_kiq_init_register()
3419 mqd->cp_hqd_pq_wptr_poll_addr_lo); in gfx_v10_0_kiq_init_register()
3421 mqd->cp_hqd_pq_wptr_poll_addr_hi); in gfx_v10_0_kiq_init_register()
3432 mqd->cp_hqd_pq_doorbell_control); in gfx_v10_0_kiq_init_register()
3436 mqd->cp_hqd_pq_wptr_lo); in gfx_v10_0_kiq_init_register()
3438 mqd->cp_hqd_pq_wptr_hi); in gfx_v10_0_kiq_init_register()
3441 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v10_0_kiq_init_register()
3444 mqd->cp_hqd_persistent_state); in gfx_v10_0_kiq_init_register()
3448 mqd->cp_hqd_active); in gfx_v10_0_kiq_init_register()
3459 struct v10_compute_mqd *mqd = ring->mqd_ptr; in gfx_v10_0_kiq_init_queue() local
3467 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v10_0_kiq_init_queue()
3479 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v10_0_kiq_init_queue()
3488 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v10_0_kiq_init_queue()
3497 struct v10_compute_mqd *mqd = ring->mqd_ptr; in gfx_v10_0_kcq_init_queue() local
3501 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v10_0_kcq_init_queue()
3509 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v10_0_kcq_init_queue()
3513 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v10_0_kcq_init_queue()